Allocation of input/output bus address space to native...

Details Allocation of input/output bus address space to native... Allocation of input/output bus address space to native...

1999-11-10

2003-02-25

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

C710S003000, C710S036000, C710S037000, C710S038000

Reexamination Certificate

active

06526459

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The invention relates generally to computer memory management techniques and more specifically to allocation of memory space for input/output (I/O) devices in a computer system.
BACKGROUND OF THE INVENTION
In traditional computer systems, such as those employing a peripheral component interconnect (PCI) bus, I/O devices are coupled to the system by a bus such as the PCI bus. Software programmed to interact with the I/O devices uses memory space allocated according to the bus standard for such interaction. For example, I/O devices on a PCI bus are allocated memory space at a specific location for interaction with the rest of the system.
FIG. 1
is a block diagram illustrating a prior art system. The system comprises software
101
, an x86 processor
102
, a north bridge
103
, a dynamic random access memory (DRAM)
104
, a display D
105
, a south bridge
106
, an input/output (I/O) device X
107
, an I/O device Y
108
, and an I/O device Z
109
. The software
101
is executed on the x86 processor
102
, which is coupled to the north bridge
103
. The north bridge
103
is coupled to the DRAM
104
and the display D
105
. The north bridge
103
is coupled to the south bridge
106
via a peripheral component interconnect (PCI) bus. The north bridge
103
provides an interface between the x86 processor
102
and the PCI bus. The I/O device X
107
, the I/O device Y
108
, and the I/O device Z
109
are also coupled to the north bridge
103
via the PCI bus. The south bridge
106
provides support for other peripheral devices, for example by providing a universal serial bus (USB) interface and an integrated drive electronics (IDE) interface. In this case, the south bridge
211
serves to couple the PCI bus to the USB interface and the IDE interface.
FIG. 4
is a diagram illustrating a prior art memory map. In four gigabytes of address space, the lower
32
megabytes is allocated as DRAM address space
401
, while the remaining address space is allocated as PCI memory address space
402
. The PCI memory address space
402
serves as memory space for interaction with I/O devices on a PCI bus. A number of disadvantages arise from allocating address space in this manner. For example, since the PCI memory address space
402
needs to be organized in a predictable manner to allow interaction with I/O devices on the PCI bus, the organization of PCI memory address space
402
is heavily constrained. It is difficult to support I/O devices that do not closely conform to the PCI standard. The rigidity of the allocation of PCI memory address space
402
also puts constraints on DRAM address space
401
and limits the expansion of DRAM address space
401
.
The x86 processor
102
accesses I/O device X
107
through a physical address X, I/O device Y
108
through a physical address Y, and I/O device Z
109
through a physical address Z. Physical addresses X, Y, and Z are located in PCI memory address space
402
. Since the prior art memory map provides only for DRAM address space
401
and PCI memory address space
402
, no support is provided for I/O devices that are not coupled through the PCI bus.
As the performance requirements for computer systems continue to increase, previously established standards for computer system design begin to impede attempts at increasing computer system performance. The limitations of the memory map of
FIG. 4
impair attempts to integrate new I/O devices into the system without using the existing PCI bus. Thus, a new technique is needed for allocating memory space to I/O devices in a computer system.


REFERENCES:
patent: 5931920 (1999-08-01), Ghaffari et al.
patent: 6061753 (2000-05-01), Ericson
patent: 6112263 (2000-08-01), Futral
patent: 6112281 (2000-08-01), Bamford et al.
patent: 6408373 (2002-06-01), Burger et al.
IBM TDB, ‘Transparent Access to Local or Remote I/O Via Various Channels and/or Links’, vol. 31, No. 6, pp. 220-227, Nov. 1988.

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