Allocating system resources based upon priority

Details Allocating system resources based upon priority Allocating system resources based upon priority

1999-05-07

2002-08-27

Thai, Xuan M. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S040000, C710S264000

Reexamination Certificate

active

06442631

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to controlling access to computer peripheral devices based upon a priority code, and more particularly, to the arbitration of requests for resources among multiple processes, processors, and peripheral devices.
2. Description of the Related Art
With the ever-increasing amount of data being processed by today's computer systems, the efficient use of computer resources is very important. The processing power of computer systems is often increased by adding processors and allowing multiple processes to run on each processor. In addition, most computers include specialized circuitry, provided via expansion boards that plug into the computer's expansion slots. Typically, these slots are supported by a standardized input/output (I/O) bus such as the Industry Standard Architecture (ISA) bus, the Extended Industry Standard Architecture (EISA) bus, and the Peripheral Component Interconnect (PCI) bus.
In current operating systems (OSs) that run multiple tasks concurrently, central processing units (CPUs) typically schedule a task based upon priority; higher priory tasks are allowed to run first and use a larger slice of the CPU's time. In single and multi-processor systems, the allocation of shared resources like buses, expansion boards and other devices is commonly on a first-come-first-served basis. Solutions for the resource allocation problem have either not used a priority based approach or have focused on the arbitration of multiple resource requests at the I/O bus level.
Today's Symmetric MultiProcessing (SMP) computer systems have begun to address the fact that different processors have multiple processes of different priority running on them. The Advanced Programmable Interrupt Controller (APIC) interrupt delivery system by Intel Corporation, Santa Clara, Calif., is capable of routing the system's interrupts to the processor with the lowest priority process running, allowing a processor with a higher priority process to continue working undisturbed.
For several decades, the Unix operating system (Unix), originally developed by AT&T, has used process priority to determine access to a computer's CPU. Another example of priority based resource allocation is Simple Network Management Protocol (SNMP), found in several OSs, like Unix, MSDOS by Microsoft Corporation, Redmond, Wash., and VMS by Digital Equipment Corporation, Maynard, Mass. SNMP utilizes high priority, or out-of-band, messages to carry control and performance information, enabling network administrators to perform administrative duties and take corrective action when a network is overloaded or deadlocked.
SUMMARY OF THE INVENTION
In a system implemented according to the invention, a bus master, such as a processor, initiates transactions on a bus and provides associated priority information for that transaction. A bus device, such as a memory controller, then receives and processes that transaction, and further receives and retains the priority information. Using this priority information, the bus device can alter the order in which it initiates or processes the transactions. For example, if the bus master assigns priority based on corresponding operating system task priority, transactions associated with low priority tasks may be deferred in favor of transactions initiated by high priority tasks.
According to one embodiment, a bus device has a transaction queue which stores the transaction request and includes storage for a priority level assigned by the process generating the transaction. This priority value could either be the same as the process priority that generates the request or selected using another scheme. A transaction and its priority level are delivered to the queue by a transaction decoder connected either to a multiplexed data bus or separate transaction and priority data buses. The transaction decoder has logic that inserts a new transaction and its priority into the queue ahead of lower priority transactions. The transaction queue has logic to ensure that the highest priority transaction is issued first. If two transactions have equal priorities, the transaction that has been in the queue longest would take precedence. Furthermore, the transaction queue has logic to periodically adjust the priority of already stored transactions to prevent transactions of low priority from being excluded completely from transaction processing during periods of high activity. There is also logic to enable a process to delete an already stored transaction and to upgrade the priority of an already stored transaction. In addition, the transaction queue has logic to resort the queue, if necessary, after an insertion or deletion of a transaction entry or the upgrade or adjustment of the priority of an already stored transaction entry.


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