Alleviating line end shortening in transistor endcaps by...

Details Alleviating line end shortening in transistor endcaps by... Alleviating line end shortening in transistor endcaps by...

2001-05-31

2003-04-22

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C430S005000

Reexamination Certificate

active

06553560

ABSTRACT:

BACKGROUND
1. Field of the Invention
The invention relates to the process of fabricating semiconductor chips. More specifically, the invention relates to a method and an apparatus that extends phase shifters to alleviate line end shortening and provide better gate critical dimension control during an optical lithography process for manufacturing an integrated circuit.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is typically used to manufacture integrated circuits. This optical lithography process generally begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are generally formed of chrome, and light-transmissive clear regions (chromeless), which are generally formed of quartz, is then positioned over this photoresist coated wafer. (Note that the term “mask” as used in this specification is meant to include the term “retical.”) Light is then shone on the mask from a visible light source or an ultraviolet light source.
This light is generally reduced and focused through an optical system that contains a number of lenses, filters and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the light is blocked by opaque regions of mask, leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, typically through chemical removal of the exposed
on-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
One problem that arises during the optical lithography process is “line end shortening” and “pullback” caused by optical effects. For example, the upper portion of
FIG. 1
illustrates a design of a transistor with a polysilicon line
102
, running from left to right, that forms a gate region used to electrically couple an upper diffusion region with a lower diffusion region. The lower portion of
FIG. 1
illustrates the actual printed image that results from the design.
Note that because of optical effects and resist pullback there is a significant amount of line end shortening. This line end shortening is due to optical effects that cause the light to expose more of the resist under a line end than under other portions of the line.
Note that polysilicon line
102
has been narrowed using optical phase shifting in order to improve the performance of the transistor by reducing the resistance through the gate region. Phase shifters are often incorporated into a mask in order to achieve line widths that are smaller than the wavelength of the light that is used to expose the photoresist layer through the mask. During phase shifting, the destructive interference caused by two adjacent clear areas on a mask is used to create an unexposed area on the photoresist layer. This is accomplished by exploiting the fact that light passing through a mask's clear regions exhibits a wave characteristic having a phase that is a function of the distance the light travels through the mask material. By placing two clear areas adjacent to each other on the mask, one of thickness t
1
and the other of thickness t
2
, one can obtain a desired unexposed area on the underlying photoresist layer caused by interference. By varying the thickness t
1
and t
2
appropriately, the light exiting the material of thickness t
2
is 180 degrees out of phase with the light exiting the material of thickness t
1
. Phase shifting is described in more detail in U.S. Pat. No. 5,858,580, entitled “Phase Shifting Circuit Manufacture Method and Apparatus,” by inventors Yao-Ting Wang and Yagyensh C. Pati, filed Sep. 17, 1997 and issued Jan. 12, 1999, which is hereby incorporated by reference.
In order to compensate for line end shortening, designers often add optical proximity correction (OPC) features, such as “hammer heads,” onto line ends. For example, in
FIG. 2A
, a hammerhead
215
is added onto an endcap
216
of a transistor in order to reduce the problem of line end shortening in some situations. However, note that hammerhead
215
may give rise the design rule violations that can potentially cause bridging between the hammerhead and polysilicon line
202
.
This bridging problem can be alleviated by introducing a separation between hammerhead
215
and polysilicon line
202
. However, introducing such a separation increases the size of the circuit element, which means that fewer circuit elements can be integrated into a semiconductor chip.
What is needed is a method and an apparatus for mitigating the line end shortening problem in transistor endcaps, while reducing the impact of OPC features, such as hammerheads.
SUMMARY
One embodiment of the invention provides a system and a method for reducing line end shortening and improved gate critical dimension control during an optical lithography process for manufacturing an integrated circuit. The system operates by receiving a specification of the integrated circuit, wherein the specification defines transistors that include gates. Next, the system identifies a gate within the specification, wherein the gate includes an endcap that is susceptible to line end shortening during the optical lithography process. The system then extends a phase shifter used to form the gate, so that the phase shifter defines at least a portion of the endcap and thereby reduces line end shortening of the endcap due to optical effects.
In one embodiment of the invention, extending the phase shifter involves extending the phase shifter past the endcap.
In one embodiment of the invention, extending the phase shifter involves extending the phase shifter so that it covers at least part of the endcap, but does not extend past the endcap. In a variation on this embodiment, the phase shifter extends past the endcap.
In one embodiment of the invention, the system automatically checks design rules that specify a minimum distance between the phase shifter and other structures within the integrated circuit.
In one embodiment of the invention, the system additionally marks the endcap to prevent subsequent optical proximity correction (OPC) of the endcap. In a variation on this embodiment, the system subsequently applies OPC to the layout, without applying OPC to endcaps that have been marked.
In one embodiment of the invention, if the endcap has been modified through optical proximity correction (OPC), the system replaces the modified endcap with an (ideal) unmodified endcap.
In one embodiment of the invention, if the endcap is not straight, the system replaces the endcap with a straight endcap.


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