All metal giant magnetoresistive memory

Details All metal giant magnetoresistive memory All metal giant magnetoresistive memory

2001-06-18

2002-11-19

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S173000

Reexamination Certificate

active

06483740

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to memory technology employing the property of giant magnetoresistance (GMR). More specifically, a memory architecture is described herein in which the memory cells and the control electronics are all implemented using multi-layer thin film elements exhibiting GMR. According to further embodiments, a unified memory architecture is provided in which multiple types of conventional memories are replaced by the memories of the present invention.
Semiconductor memory technology, and specifically silicon random access memories (RAMs), are an important part of the foundation of all data processing systems. The device density of silicon technology has increased steadily in the decades since its introduction and, until recently, roughly conformed to Moore's law which states that the device density of silicon chips doubles every eighteen months. That is, in recent years, the rate at which the bit density of silicon memories has improved has increasingly fallen short of the rate predicted by Moore's law. The limitations of semiconductor technology are readily apparent in the widening gap between its future potential and its past performance. There are a number of reasons for this.
First, the limitations of semiconductor technology with regard to device size have not, and in many cases cannot, keep up with advances in lithography techniques. For example, as the feature size of silicon devices shrinks, undesirable effects occur including the loss of information through charge leakage, high oxide breakdown, and power consumption problems. Inherent limitations such as the non-scalability of p-n junctions and charge pumps also translates into an inability to take full advantage of advances in lithography.
Memory systems which include mechanical elements, e.g., disk drives, are also facing technological obstacles relating to storage density such as, for example, the difficulty of mechanically aligning a read head with increasingly smaller storage locations on a magnetic storage medium. Access times for such memories are also typically orders of magnitude greater than that of the semiconductor memories which they complement. Such memories are also vulnerable to a variety of environmental stresses including, for example, shock, vibration, temperature extremes, radiation, etc. In combination, such limitations impede the dual objectives of greater information density and faster information access.
The evolution of memory technologies such as FLASH and EEPROM have addressed some of these limitations in that they have much faster access time than conventional magnetic memories and are more resistant to some environmental stresses, e.g., mechanical shock. However, these “hardcard” technologies do not have sufficient storage density or capacity to support the average stand-alone or networked computer system. Indeed, with one-tenth the capacity of standard disks, FLASH and EEPROM provide only supplemental storage capacity and have the added disadvantage of a limited number of access cycles. Moreover, although FLASH and EEPROM access times are better than those of conventional mechanical systems, they are clearly inferior as compared to DRAM or SRAM access times. In addition, the high power consumption per megabyte associated with FLASH and EEPROM necessitates larger power supplies, obviating the hardcard technologies' advantage in size and weight. Therefore, although FLASH and EEPROM provide advantages with regard to speed and reliability, these memory technologies cannot achieve the capacity or power efficiency of conventional magnetic disk drives.
More recently, there has been a significant shift in industry-wide memory development aimed at replacing both solid-state semiconductor memories and mechanical storage by magnetic RAM. Most of this activity has focused on hybrid magnetic RAMs, known generically as MRAM, in which a magnetic memory array is combined with semiconductor electronics.
It is therefore desirable to develop memory technologies which can take advantage of advances in lithography techniques without suffering from the limitations inherent in semiconductor memories, and which can take full advantage of recent developments in GMR electronics. It is also desirable to that such technologies overcome the limitations of mechanical memory systems.
SUMMARY OF THE INVENTION
According to the present invention, a memory technology is provided which is based on structures which exhibit the property of giant magnetoresistance (GMR), and which overcomes the limitations of conventional memories described above. The memory arrays of the present invention include individual memory cells comprising GMR thin film structures which store one or more bits of information in their magnetic layers. Memory access lines are configured to provide random access to each cell in an array. Selection matrices, control electronics, preamplifiers, and sense amplifiers are all implemented with an all metal device referred to herein as a “transpinnor.” The transpinnor is a network of GMR thin film structures which has characteristics like both a transistor and a transformer.
The performance of GMR structures improves as the feature size decreases. In addition, production costs associated with the all metal memories described herein will be dramatically lower than those associated with semiconductor memories for a number of reasons.
First, because the GMR structures of the invention are relatively simple, the number of fabrication steps is significantly reduced as compared to the typical semiconductor process for a similar device (e.g., fewer than 10 versus greater than 30). Second, the process steps for the all metal architecture of the present invention are carried out at relatively low temperatures (e.g., 200° C.) as compared to the high temperature processing by which semiconductor techniques are characterized (e.g., 800° C.). Furthermore, hybrid magnetic RAMs involve both processing methods, with subsequent bonding of the semiconductor support electronics with the magnetic memory array. In contrast, an all-metal magnetic RAM may be fabricated as a single monolithic integrated circuit using a single mask set because the GMR electronics and the GMR memory array are made of the same materials.
In addition, implementation of the memory electronics using transpinnors is advantageous because they can be deposited and patterned at the same time as the memory elements rather than sequentially as with semiconductor process, thereby further reducing the number of process steps required. The all metal architecture of the present invention will also be more immune to radiation than semiconductor or hybrid magnetic RAM memories. Moreover, transpinnor circuits tend to take up less area than equivalent semiconductor circuits (the transpinnor-based differential sense amplifier is a good example).
Additionally and according to various specific embodiments, an all-metal magnetic RAM can be a low-power device, in part because of the inherently low power of GMR circuitry, in part because a single transpinnor can perform multiple digital functions, and in part because of the ability of GMR circuits to turn off those subsystems that are not in use.
Finally, because the memory technology of the present invention is persistent, i.e., no refresh or standby power is required to retain stored information, it may be used not only to replace RAM, but mechanical storage systems as well.
According to a specific embodiment, a unified memory architecture is provided in which each of a plurality of memory types in the architecture are implemented using a specific embodiment of the memory arrays of the present invention. A specific example of such an architecture is described in the context of a computer memory architecture in which both system memory and long term storage are implemented according to the present invention.
Thus, the present invention provides methods and apparatus relating to a memory device comprising memory cells, access lines, and support electronics for faci

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