All-digital symbol clock recovery loop for synchronous...

Details All-digital symbol clock recovery loop for synchronous... All-digital symbol clock recovery loop for synchronous...

2011-06-14

2011-06-14

Phu, Phuong (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S371000, C375S373000, C375S376000

Reexamination Certificate

active

07961832

ABSTRACT:
A symbol clock (16) associated with a symbol stream (5) in a synchronized communication receiver can be recovered by adjusting the phase of a symbol clock signal (12). The phase adjustment is accomplished by applying a digitally controlled delay (13) to the symbol clock signal based on a timing relationship between the symbol clock and symbol transitions (17) in the symbol stream.

REFERENCES:
patent: 5646968 (1997-07-01), Kovacs et al.
patent: 6795514 (2004-09-01), Gresham
patent: 6934869 (2005-08-01), Bhoja et al.
Data sheet for Philips OQ2541HP; OQ2541U SDH/SONET Data and Clock Recovery Unit, May 27, 1999, 35 pgs.
“U.S. Appl. No. 09/790,861, filed Feb. 23, 2001”.

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