All digital phase-locked loop with widely locked frequency

Details All digital phase-locked loop with widely locked frequency All digital phase-locked loop with widely locked frequency

2008-07-10

2011-11-01

Corrielus, Jean B (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S375000, C327S156000, C327S159000

Reexamination Certificate

active

08050376

ABSTRACT:
An all-digital phase-locked loop (ADPLL) composed of digital circuits is provided. The ADPLL includes a phase-frequency detector (PFD), a control unit, a digital controlled oscillator (DCO), and a plurality of frequency dividers. A first frequency divider divides a frequency of a feedback signal CKOUTby a natural number M to generate a first output signal CKOUT/M. The PFD generates a decrement signal dn and an increment signal up, based on a phase difference and a frequency between a first reference clock signal CKINand the first output signal CKOUT/M. The DCO generates a clock signal CKDCObased on the digital control signals. A second frequency divider receives the digital control signals from the control unit and the CKDCOfrom the DCO and divides the frequency of the CKDCOby a bit number of the digital control signals to generate a feedback signal CKOUTto the first frequency divider.

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