Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements
Reexamination Certificate
2006-06-30
2008-09-16
Pascal, Robert J. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Afc with logic elements
C331S017000, C375S376000
Reexamination Certificate
active
07425874
ABSTRACT:
A digital audio system including a digital phase-locked-loop circuit for generating a pulse-width-modulation (PWM) clock signal, applied to a pulse-code-modulation to pulse-width-modulation converter, is disclosed. The digital phase-locked loop includes a phase detector for measuring phase error between a reference signal and a feedback signal. A digital version of the phase error, after filtering by a loop filter, is converted to a digital delay control word that is sampled at twice its frequency. Successive samples of the delay control word control the propagation delay of first and second delay cells in an oscillator. The use of successive samples at substantially twice the frequency of change of the delay control word effectively realizes the sum of a sinc filter and a comb filter, which greatly suppresses the effects of jitter in the reference signal to the digital phase-locked loop.
REFERENCES:
patent: 5459766 (1995-10-01), Huizer et al.
patent: 6069505 (2000-05-01), Babanezhad
patent: 7282999 (2007-10-01), Da Dalt et al.
patent: 2002/0135419 (2002-09-01), Groves et al.
patent: 2003/0141936 (2003-07-01), Staszewski et al.
patent: 2004/0155714 (2004-08-01), Nishikawa et al.
Dunning et al., “An All-Digitial Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors”, Apr. 1995, IEEE Journal of Solid-State Circuits, vol. 30, No. 4, pp. 412-422.
Dai et al., Design of High-Performance CMOS Voltage-Controlled Oscillators (Klewer Academic, 2002), pp. 88-106.
Olsson et al., “An all-Digital PLL Clock Multiplier”, 2002 IEEE Asia-Pacific Conference on ASIC Proceedings, Paper 5B-3.
Best, Phase-Locked Loops, 3d ed. (McGraw-Hill), 1997), pp. 177-199.
Barrett, “Fractional/integer-N PLL Bascis”, Technical Brief SWRA029 (Texas Instruments, Aug. 1999).
Gilbert, “The Multi-Tanh Principle: A Tutorial Overview”, J. Solid State Circ., vol. 33, No. 1 (IEEE, Jan. 1998), pp. 2-17.
Angilivelil Josey George
Risbo Lars
Shankar Asit
Brady III Wade J.
Franz Warren L.
Johnson Ryan J.
Pascal Robert J.
Telecky , Jr. Frederick J.
LandOfFree
All-digital phase-locked loop for a digital pulse-width... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with All-digital phase-locked loop for a digital pulse-width..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and All-digital phase-locked loop for a digital pulse-width... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3992655