Alignment of memory read data and clocking

Details Alignment of memory read data and clocking Alignment of memory read data and clocking

2007-01-18

2008-08-05

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S189050, C365S233100

Reexamination Certificate

active

07408822

ABSTRACT:
Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To align data and clock signals when needed, delay is added to the output clock signal during the read operation. This alignment allows various timing specifications to be met when they would otherwise be violated, therefore improving data integrity in the system.

REFERENCES:
patent: 6385129 (2002-05-01), Silvestri

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