Alignment of instructions and replies across multiple...

Details Alignment of instructions and replies across multiple... Alignment of instructions and replies across multiple...

2003-10-08

2009-12-15

Kindred, Alford (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

Reexamination Certificate

active

07634597

ABSTRACT:
Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.

REFERENCES:
patent: 5640515 (1997-06-01), Park
patent: 5673396 (1997-09-01), Smolansky et al.
patent: 5930359 (1999-07-01), Kempke et al.
patent: 5956492 (1999-09-01), Jander et al.
patent: 5978355 (1999-11-01), Yamaguchi
patent: 6233250 (2001-05-01), Liu et al.
patent: 6606666 (2003-08-01), Bell et al.
patent: 7058757 (2006-06-01), Branth et al.
patent: 2004/0022082 (2004-02-01), Khanna
patent: 2004/0024960 (2004-02-01), King et al.
patent: 2007/0299993 (2007-12-01), Vorbach et al.
Vorbach et al., WO02071249, Method and Devices for Treating and/or Processing Data—(machine translation), pp. 9-10.

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