Alignment mode selection mechanism for elastic interface

Details Alignment mode selection mechanism for elastic interface Alignment mode selection mechanism for elastic interface

2005-02-11

2008-10-28

Kim, Kevin Y (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C713S401000

Reexamination Certificate

active

07443940

ABSTRACT:
Methods and apparatus are disclosed for aligning received data bits in elastic interface systems. Depending upon which one of several alignment modes is selected, data bits can be loaded into FIFO latches on rising clock edges if the data was sent on rising clock edges, on falling clock edges if the data was sent on falling clock edges, or on the nearest clock edge if minimum latency is desired. Alternatively, data bits can be delayed by one or more bit times before loading into FIFO latches to reduce the elastic interface system's sensitivity to drift. The present invention permits a user to trade off factors related to for latency, drift, and skew by choosing among different alignment modes in an elastic interface system.

REFERENCES:
patent: 6400642 (2002-06-01), Mehrotra et al.
patent: 6603706 (2003-08-01), Nystuen et al.

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