Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-03-29
2002-11-12
Lam, Tuan T. (Department: 2816)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06481003
ABSTRACT:
DESCRIPTION
1. Technical Field
The present invention relates to an alignment method and a method for producing a device using the alignment method, which is suitable for application to the case where, in a projection exposure apparatus which sequentially transfers a pattern image of a reticle onto each shot area on a wafer according to array coordinates predicted for example using a statistical technique, the reticle and each shot area on the wafer are sequentially aligned.
2. Background Art
A projection exposure apparatus by which a pattern image of a photomask or reticle (hereafter generically called “reticle”) is projected onto each shot area on an exposure substrate through a projection optical system, is used at the time of manufacturing semiconductor elements or liquid crystal display elements or the like by a photolithography process. In recent years, as this kind of projection exposure apparatus, an exposure apparatus of a so-called step—and—repeat method, for example a reduction projection type exposure apparatus (stepper), is often used, where an exposure substrate is mounted on a stage which is movable in two dimensions, and the exposure substrate is stepped by this stage, and an operation for sequentially exposing the pattern image of the reticle onto each shot area on the exposure substrate is repeated.
For instance, considering a semiconductor element, because circuit patterns of many layers are formed by superposing on a wafer spread with photosensitive material and serving as the exposure substrate, when the circuit patterns of the second and subsequent layers are projection exposed on the wafer, it is necessary to accurately perform alignment of each shot area on the wafer where the circuit pattern has already been formed, with a pattern image of the reticle which is to be exposed thereafter, that is, alignment of the wafer and reticle.
Conventional wafer alignment methods for steppers and the like, are in general as follows (refer for example to Japanese Unexamined Patent Application, First Publication No. 61-44429, and corresponding U.S. Pat. No. 4,780,617).
That is, chip patterns which contain a mark for alignment (alignment mark) are respectively formed on multiple shot areas regularly arranged according to previously set array coordinates on a wafer which becomes the substrate to be processed.
First of all, previously determined alignment marks formed on a prescribed number of shot areas, are detected inside a plurality of shot areas on the wafer, and statistical processing is performed based on this detection result to calculate each position of all the shot areas on the wafer. Then alignment of the wafer is performed based on the calculation result.
In this method, the alignment mark need not be detected for all the shot areas formed on the wafer, and the efficiency of processing is improved.
However, even if the wafer is stepped based on the array coordinates set using this alignment method, satisfactory superpositioning accuracy is not necessarily obtained due to the errors in the wafer error movement mechanism or errors in the reduction ratio of the optical system for projecting the circuit pattern.
Therefore, a method for correcting these errors (hereafter, called wafer errors) has also been contrived (hereunder, this method is called the wafer error correction method). In the wafer error correction method, the measurement result is corrected by operation.
When the wafer error correction method is used, measurement of the alignment mark formed in the shot area, may involve, in the case where the shape of the alignment mark is for example a cross shape, measuring one alignment mark for each shot area (hereafter, called the alignment shot area) where the alignment mark is detected.
Then, the obtained measurement result is corrected by a prescribed operational expression to correct the wafer error, and the position of the shot area where the measurement is not performed is calculated using the measurement result after correction.
Consequently, when this method is used, the error can be corrected without an increase in measurement time, and hence superposition accuracy is improved.
However in this method, only errors of the entire wafer can be corrected, and errors in misregistration or shape of each shot (hereafter, called shot error) cannot be corrected.
Recently, a method for correcting this shot error has also been contrived (hereunder, this method is called the shot error correction method). In the shot error correction method, a plurality of alignment marks formed in the alignment shot area is measured. In the case where this method is used, then for one alignment shot area, when the shape of the alignment mark is for example cross shape, it is necessary to measure at least three points.
In the shot error correction method, at first a plurality of alignment marks is measured, and the obtained measurement result is corrected using a prescribed operational expression (this operational expression is different from the operational expression used in the aforementioned wafer error correction method), and the displacement of the alignment mark from a design value is calculated, and errors in the misregistration and shape for each shot area are corrected based on the calculation result. In this manner, in the shot error correction method, misregistration etc. for each shot area can be measured, and wafer misregistration and the like can be measured.
Therefore, the shot error correction method can perform alignment to a higher accuracy than that for the wafer error correction method.
However, while highly accurate alignment can be performed when, as described above, the shot error correction method is used, it is necessary to measure a plurality of alignment marks for the alignment shot area (at least three points when the alignment mark shape is cross shape). Hence if this measurement is performed for each wafer, a decrease in throughput is incurred.
On the other hand, when the wafer error correction method is used, only one alignment mark in the alignment shot area need be measured, but while throughput is high, alignment accuracy is low.
Recently, further densification of integrated circuits is demanded. For example, for CPUs (central processing units) used in personal computers, ones with a wiring width of 0.35 &mgr;m have been put to practical use, and in the near future plans for a wiring width of 0.25 &mgr;m have been announced. Therefore, it is considered that precise processing technology at even higher densities will be demanded in the future. To answer the demand for such densification, improvement in alignment accuracy becomes extremely important.
Moreover, also in liquid crystal display devices, those which have an even greater number of pixels are required. To answer this demand also, an improvement in alignment accuracy becomes important.
However, there is a problem in that when as mentioned above, the shot error correction method which improves alignment accuracy is used, throughput inevitably decreases.
DISCLOSURE OF INVENTION
The present invention takes into consideration the abovementioned circumstances, with the object of providing an alignment method and a method for producing a device using this method, where, in a method for performing alignment of each shot area on an exposure substrate with a reticle according to array coordinates predicted using a statistical technique, alignment accuracy can be improved without incurring a decrease in throughput.
To solve the abovementioned problems, the present invention, in an alignment method for determining for each of N (N≧2) substrates, exposure position information for a plurality of areas on the substrates to which a pattern of a mask is transferred, involves the steps of:
detecting a plurality of marks on an nth substrate (1≦n≦N−1), and in order to determine exposure position information for a plurality of areas on the nth substrate using a first model function, determining first and second parameters of the first model function using position information of the detected
Lam Tuan T.
Nguyen Long
Nikon Corporation
Oliff & Berridg,e PLC
LandOfFree
Alignment method and method for producing device using the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Alignment method and method for producing device using the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Alignment method and method for producing device using the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2944960