Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2002-08-13
2003-12-09
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S665000, C257S774000, C257S750000
Reexamination Certificate
active
06661106
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to processes for the manufacture of semiconductor devices, and more particularly to an alignment mark structure for ultraviolet laser fusing, and a method for applying the alignment mark structure during semiconductor device manufacture.
2. Related Art
Metal link fuses are used in semiconductor integrated circuit devices to provide redundancy, electrical chip identification, and customization of wiring. For integrated circuits having three or more layers of wiring, the metal link fuses are typically formed from a segment of one of the wiring layers, e.g., the “last metal” or “last metal minus one” wiring layer. Fusing, i.e., deletion of a segment of metal link fuse line, is accomplished by exposing the segment to a short, high intensity pulse of light from a laser. The metal link fuse line absorbs energy, melts and expands, and ruptures any overlayer passivation material. The molten metal boils or vaporizes out of, and off of, its dielectric surroundings, disrupting the continuity of the metal link fuse line and causing high electrical resistance. An electrical sensing circuit is used to detect fuse segment resistance.
To improve silicon utilization, both metal fuse link size and the distance between adjacent metal fuse links must be minimized. Two of the limitations to minimizing these parameters are the diameter of the laser beam (n.b., the minimum diameter is about twice the wavelength) and the positioning accuracy of the laser beam relative to the metal fuse link. The use of lasers having shorter wavelengths achieves decreasing laser beam diameter, but positioning accuracy is driven by the ability of the laser to accurately determine the positions of relevant structural topographies, known as alignment marks. An alignment mark is an image selectively placed within or outside an array for either testing or aligning purposes, and is also known as an alignment key or an alignment target. The term “alignment,” as used herein, refers to the mechanical positioning of coordinate points on a wafer substrate relative to the laser beam used to delete the metal fuse link. Accurately determining the position of an alignment mark requires that there be a high contrast between the alignment mark and the surrounding dielectric material.
SUMMARY OF THE INVENTION
It is therefore a feature of the present invention to overcome the above shortcomings related to incorrect determination of alignment marks, by providing an alignment mark structure having multiple thicknesses of dielectric material (i.e., multiple optical path lengths) over the alignment mark and in the adjacent dielectric. This approach is particularly useful for integrated circuit designs employing copper metallurgy and organic dielectric films, and provides yield enhancement at the end of the fabrication process, the very spot where yield loss is most expensive.
The present invention eliminates fusing problems due to the incorrect determination of the alignment mark position (or center line), in alignment processes using laser beams having characteristic wavelengths in the ultraviolet region, e.g., wavelengths <380 nm, by formation of a unique alignment mark structure. The alignment mark structure is comprised of a metal link fuse alignment mark structure which is surrounded and covered by one or more dielectric films, and where the alignment mark structure is composed of a substantially vertical stack of at least two metal wiring layers or levels. For example, one segment of the alignment mark structure can be formed at the last metal wiring layer (LM), and another segment of the alignment mark structure can be formed at the previous metal wiring layer (LM-1). The present invention is also drawn to a method of utilizing the alignment mark structure disclosed herein. By forming parts of the alignment mark structure at different metal wiring levels, the optical path lengths adjacent the alignment mark structures and over the alignment mark structures are different for each alignment mark structure position, thus minimizing the possibility of there being a low difference in the reflected energy (i.e, low contrast or “low visibility”) between the metal link fuse and the surrounding dielectric material. In practice, the laser beam scanning apparatus of the fusing tool is programmed to look at the LM layer of the alignment mark structure first, and if there is insufficient or low contrast, then to look at the LM-1 layer of the alignment mark structure. Contrast can be defined as the range of light and dark values in a picture, or the ratio between the maximum and the minimum brightness values. Insufficient or low contrast is shown mainly as shades of gray, while high contrast is shown as blacks and whites with very little gray.
In a first general aspect, the present invention provides a semiconductor device structure that acts as an alignment mark structure for laser fusing.
In a second general aspect, the present invention provides a semiconductor integrated circuit device containing an alignment mark structure for laser fusing using a laser having a characteristic wavelength, said alignment mark structure comprising: a first metal wiring layer formed in a first layer; and a second metal wiring layer formed in a second layer, said second layer overlaying the first layer.
In a third general aspect, the present invention provides a system for aligning a semiconductor integrated circuit device for laser fusing, said system comprising: an alignment mark structure formed within at least two layers of said semiconductor integrated circuit device, said alignment mark structure containing at least one alignment mark and formed from a plurality of metal wiring layer segments distributed throughout said at least two layers and surrounded by a first material; a scanning device comprising a laser beam, said scanning device capable of targeting said laser beam at a surface of said semiconductor integrated circuit device beneath which said alignment mark structure is located; a device for determining the reflected energy from said alignment mark structure and said surrounding first material; and a device for accurately determining the position of said alignment mark structure from said reflected energy.
In a fourth general aspect, the present invention provides a method of making an alignment mark structure for use with a laser fusing device, said method comprising the steps of: a) providing a substrate layer; b) depositing a base layer on said substrate layer; c) depositing a first layer on said base layer; d) forming a first metal wiring layer in said first layer; e) depositing a second layer on said first layer and said first metal wiring layer; and f) forming a second metal wiring layer on said second layer.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of embodiments of the invention.
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Gilmour Richard A.
Klaasen William A.
Motsiff William T.
Clark Jasmine
Sabo William D.
Schmeiser Olsen & Watts
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