Alignment mark and exposure alignment system and method...

Details Alignment mark and exposure alignment system and method... Alignment mark and exposure alignment system and method...

2005-05-03

2005-05-03

Hu, Shouxiang (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C438S975000

Reexamination Certificate

active

06888261

ABSTRACT:
An alignment mark and an exposure alignment system and method using the alignment mark for aligning wafers are described. The alignment mark is formed of a plurality of mesa or trench type unit marks that are aligned in an inline pattern within an underlying layer under a layer to which a chemical mechanical polishing process is applied to form an alignment signal during an alignment process, thereby preventing a dishing phenomenon caused by the chemical mechanical process.

REFERENCES:
patent: 5601957 (1997-02-01), Mizutani et al.
patent: 5917604 (1999-06-01), Dirksen et al.
patent: 6255189 (2001-07-01), Muller et al.
patent: 6285455 (2001-09-01), Shiraishi
patent: 2000-0047405 (2000-08-01), None
Silicon Processing for the VLSI Era, vol. 1: Process Technology, published in 1986 by Lattice Press of Sunset Beach, California, pp. 459-473.

Affiliated with

Also associated with

Rating

Alignment mark and exposure alignment system and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Alignment mark and exposure alignment system and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Alignment mark and exposure alignment system and method... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3389517