Alignment key structure in a semiconductor device and method...

Details Alignment key structure in a semiconductor device and method... Alignment key structure in a semiconductor device and method...

2006-04-19

2009-08-11

Smith, Matthew S. (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257S758000, C438S106000

Reexamination Certificate

active

07573142

ABSTRACT:
An alignment key structure in a semiconductor device is provided. The alignment key structure includes an insulation layer formed on a substrate, and a passivation layer pattern formed on the insulation layer. The insulation layer includes a plurality of metal wirings. The passivation layer pattern includes a first opening that exposes at least one of the metal wirings. Moreover, the first opening has a width which is narrower than a width of the exposed metal wiring.

REFERENCES:
patent: 6228743 (2001-05-01), Chen et al.
patent: 7223693 (2007-05-01), Choi et al.
patent: 7265050 (2007-09-01), Choi et al.
patent: 2006/0060945 (2006-03-01), Cho et al.
patent: 2006/0138673 (2006-06-01), Kim
patent: 2008/0203590 (2008-08-01), Kang et al.
patent: 2001-127240 (2001-05-01), None
patent: 1020040053451 (2004-06-01), None

Affiliated with

Also associated with

Rating

Alignment key structure in a semiconductor device and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Alignment key structure in a semiconductor device and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Alignment key structure in a semiconductor device and method... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4060804