Aligning and offsetting bus signals

Details Aligning and offsetting bus signals Aligning and offsetting bus signals

2001-12-21

2004-07-06

Thai, Xuan M. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C713S401000, C713S600000

Reexamination Certificate

active

06760803

ABSTRACT:

FIELD
The subject matter herein relates to deskewing and offsetting electronic signals, such as multiple signals transmitted in parallel over a computer bus.
BACKGROUND
When multiple synchronized signals are transferred from one device to another across a bus system (i.e. parallel bus signals), the signals may lose their synchronization, or become “skewed.” It is, therefore, necessary to “deskew” and “resynchronize” the signals. It is also often necessary to offset the signals by a desired amount for certain timing requirements of the circuitry. A variety of deskew, synchronization, alignment and offset techniques have been developed for a variety of applications or situations. General requirements for such techniques are that they be relatively fast, error-free, easy to design and simple to implement or manufacture in an integrated circuit (IC) chip.
It is with respect to these and other background considerations that the subject matter herein has evolved.
SUMMARY
The subject matter described herein involves a bus interface and a receiver in the bus interface that receives signals from a computer bus and deskews and synchronizes the signals into valid data and control signals for use by the bus interface or a bus device of which the bus interface is a component. In a particular embodiment, the computer bus is a SCSI (Small Computer System Interface) bus, the standards for which specify a number of data and parity signals (e.g. 18 data/parity signals) and “request” and “acknowledge” signals that must be synchronized upon receipt in order to establish valid useable signals for transferring information. In a SCSI environment, the data and parity signals are typically latched on the edges of the request or acknowledge signal. Therefore, according to the subject matter herein, the data and parity signals are initially synchronized to the request or acknowledge signal and then the request or acknowledge signal is offset to ensure that the data and parity signals have sufficient time to stabilize before being latched on the edges of the request or acknowledge signal.
Generally, the signals are fed through delay logic, which adds or subtracts delay to or from each signal to synchronize the signals. In a particular embodiment the delay logic includes a series of delay units (buffers or inverters) through which the signals are passed. “Taps” are located before or after each of the delay buffers at which the signals may be read with different amounts of delay.
Thus, by reading the signal at different taps, delay may be added to or subtracted from the signal.
In a particular embodiment, the amount of the offset for the request or acknowledge signal is determined by offset logic that uses the same type of circuitry used in the delay logic, e.g. the delay buffers or inverters. The performance of the delay buffers, i.e. the period of the delay, is dependent on temperature, voltage and other conventional characteristics, parameters or environmental conditions of an IC incorporating the bus interface and the delay logic. Thus, the delay period, or performance characteristic, for one delay buffer in the offset logic is about the same as for one delay buffer in the delay logic.
The delay buffers for the offset logic are arranged in a conventional ring oscillator, which thus produces a signal having a period dependent on the performance characteristics of the delay buffers. The ring oscillator signal is used to clock a counter for a known period of time. The counter thus produces a total count at the end of the known period of time that is directly related to the performance characteristics of the delay buffers in both the offset logic and the delay logic. The known period of time and the number of delay buffers in the offset logic are selected so that the resulting count of the counter is directly related (e.g. by an integer multiple) to the number of delay periods (one per delay buffer) that need to be added to the request or acknowledge signal to offset the request or acknowledge signal sufficiently to ensure that the data and parity signals have time to stabilize before being latched on the edges of the request or acknowledge signal.
For example, in a current version of the SCSI standards, the request and acknowledge signals generally have 6¼ nanoseconds between rising and falling edges. Thus, after the data and parity signals have been synchronized to the request or acknowledge signal, the delay added to the request or acknowledge signal may be about one-half of the time between the rising and falling edges (e.g. 3⅛ nanoseconds), so the data and parity signals have about this much time to stabilize before being latched.
A more complete appreciation of the present disclosure and its scope, and the manner in which it achieves the above noted improvements, can be obtained by reference to the following detailed description of presently preferred embodiments taken in connection with the accompanying drawings, which are briefly summarized below, and the appended claims.


REFERENCES:
patent: 4495570 (1985-01-01), Kitajima et al.
patent: 5371880 (1994-12-01), Bhattacharya
patent: 5644787 (1997-07-01), Nakamura et al.
patent: 5832308 (1998-11-01), Nakamura et al.
patent: 6255878 (2001-07-01), Gauvin et al.
patent: 6256695 (2001-07-01), Williams

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