Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-04-08
2001-10-23
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06307390
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an aligner and, more specifically, to an aligner used for inspecting a number of semiconductor elements formed on a semiconductor wafer by one operation.
The present invention corresponds to that of Japanese Patent Application No. 10-54423 which has recently been filed by the same inventors as those of the present invention, and relates to an aligner wherein a contactor is brought into contact with a wafer holding member, which holds a semiconductor wafer, by vacuum adsorption to integrate the semiconductor wafer, contactor and wafer holding member into one piece.
In semiconductor inspection, electric characteristics of semiconductor elements (each referred to as a chip hereinafter) formed on a semiconductor wafer (referred to as a wafer hereinafter) are tested to screen defect-free chips. The defect-free chips are packaged with synthetic resin or ceramics in an assembly step. In a reliability test, a temperature stress or an electrical stress is applied to the packaged chips to detect a latent defect and the like. If a defective chip is detected, it is eliminated.
Chips are decreased in size and increased in packing density as electrical appliances become smaller and more functional. Recently various mounting techniques for making semiconductor products smaller have been developed. In particular, a technique of mounting a chip as a so-called bare chip without being packaged is developed. In order to put bare chips on the market, their quality assurance is required. For the quality-assured bare chips, they should take a reliability test to put them on the market. A probe apparatus can be used for the reliability test; however, in this case, bare chips have to be tested one by one. Since, moreover, a long time is required for testing one bare chip, the reliability test using the probe apparatus has a problem of costs. To inspect bare chips using a conventional reliability test apparatus, various difficulties such as electrical connection between a bare chip and a socket have to be resolved. Since a bare chip is small, its handling is considerably complicated and its inspection costs are increased.
A technique of conducting a reliability test on a plurality of wafers at once, is proposed in, for example, Jpn. Pat. Appln. KOKAI Publications Nos. 7-231019, 8-5666 and 8-340030.
Conventionally, in order to bring a plurality of contact terminals of a contact into contact with a plurality of chips formed on a wafer, the contact and wafer are arranged opposite to each other, and the contact terminals are visually aligned with their corresponding electrode pads of the wafer (hereinafter referred to as alignment) and brought into contact with the chips together. For this reason, a long time is required for the alignment, which reduces operation efficiency and applies a great load to an operator, thereby causing variations in alignment precision. As described above, the conventional alignment has the problem in which it is difficult to bring a plurality of contact terminals of a contactor into stable contact with a plurality of chips formed on a wafer.
In the foregoing Japanese Patent Application No. 10-54423, the inventors of the present invention proposes the following aligner as an alignment apparatus. A wafer holding member for holding a wafer by vacuum adsorption (hereinafter referred to as a wafer chuck) is moved in X, Y, Z and &thgr; directions to align the wafer and contactor with each other. The contactor is then placed into contact with the wafer chuck by vacuum adsorption to integrate the contactor, wafer chuck and table into one piece. However, the aligner does not have a mechanism for checking vacuum adsorption among the wafer chuck, wafer and contactor or a mechanism for checking vacuum pressure among them. For this reason, it has recently been recognized that if the vacuum adsorption is lowered, electrical contact between the wafer and contactor becomes poor during the reliability test and, in extreme cases, the integrated wafer chuck, wafer and contactor are likely to separate from each other.
BRIEF SUMMARY OF THE INVENTION
The present invention has been developed in order to resolve the above problems. It is accordingly an object of the present invention to provide an aligner capable of confirming whether a vacuum leak occurs among a wafer chuck, a semiconductor wafer and a contactor.
According to a first aspect of the present invention, there is provided a method of carrying out a test on electric characteristics of plural semiconductor elements formed on a semiconductor wafer, the method comprising:
placing a wafer holding member on a table and holding the wafer holding member thereon by vacuum adsorptivity;
placing the semiconductor wafer on the wafer holding member and holding the semiconductor wafer thereon by vacuum adsorptivity;
bringing a contactor into contact with the semiconductor wafer held on the wafer holding member, and holding the contact on the wafer holding member by vacuum adsorptivity;
confirming the vacuum adsorptivity by which the contactor and the semiconductor wafer are held on the wafer holding member, using a pressure detector;
releasing the vacuum adsorptivity by which the wafer holding member is held on the table, and allowing an aligner, which is formed by integrating the wafer holding member, the semiconductor wafer and the contactor into one piece by the vacuum adsorptivity, to move from the table; and
transporting the aligner to a test apparatus to carry out the test on the electric characteristics of the plural semiconductor elements formed on the semiconductor wafer.
According to a second aspect of the present invention, there is provided an aligner comprising:
a contactor having a plurality of contact terminals for bringing the contactor into contact with a semiconductor wafer;
a wafer holding member including a first vacuum holding mechanism for holding the semiconductor wafer by vacuum adsorptivity and a second vacuum holding mechanism for holding the contactor by vacuum adsorptivity;
a table having a third vacuum holding mechanism for holding the wafer holding member by vacuum adsorptivity; and
at least one pressure gauge connected to the first vacuum holding mechanism, the second vacuum holding mechanism, and the third vacuum holding mechanism,
wherein the pressure gauge detects a pressure of at least one vacuum holding mechanism in the first vacuum holding mechanism, the second vacuum holding mechanism, and the third vacuum holding mechanism, thereby confirming a vacuum adsorbing state in the vacuum holding mechanism.
Preferably, each of the first vacuum holding mechanism and the second vacuum holding mechanism includes:
a vacuum adsorbing internal channel provided in the wafer holding member;
a vacuum adsorbing groove formed in a surface of the wafer holding member on which the semiconductor wafer and the contactor are placed, and connected to the vacuum adsorbing internal channel;
a valve mechanism connected to the vacuum adsorbing internal channel; and
a selector valve connected to the valve mechanism, for selectively connecting the valve mechanism to one of a vacuum exhaust apparatus, an air-open apparatus and an air-close apparatus.
Preferably, the selector valve of the second vacuum holding mechanism includes a first selector valve and a second selector valve, and the first selector valve selectively connects the valve mechanism to one of the air-close apparatus and the second selector valve, and the second selector valve selectively connects the first selector valve to one of the vacuum exhaust apparatus and the air-open apparatus.
Preferably, the vacuum adsorbing groove of the second vacuum holding mechanism includes a first ring-shaped groove for adsorbing the semiconductor wafer and a second ring-shaped groove for adsorbing the contactor.
Preferably, the first selector valve and the second selector valve are each a three-port solenoid valve.
Preferably, the valve mechanism of each of the first vacuum holding mechanism and the second vacuum holding mechanism incl
Akaike Yutaka
Kono Isao
Sano Satoshi
Kerveros J
Metjahic Safet
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Tokyo Electron Limited
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