Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-23
2007-10-23
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
11066041
ABSTRACT:
A method for defining an aligned logic cell grid and interconnect layout of a semiconductor integrated circuit having a logic cell is disclosed. The interconnect layout is resized in accordance with a highest common denominator of an initial routing pitch of the interconnect layout and a transistor pitch of the logic cell. The cell grid is aligned with the resized routing pitch which provides efficient routing density and transistor performance, minimizes excess transistor area and wire routing waste while maximizing cell packing density.
REFERENCES:
patent: 5341310 (1994-08-01), Gould et al.
patent: 5754826 (1998-05-01), Gamal et al.
patent: 5977574 (1999-11-01), Schmitt et al.
patent: 6629308 (2003-09-01), Baxter
patent: 7073154 (2006-07-01), Garrison et al.
patent: 7205191 (2007-04-01), Kobayashi
patent: 2002/0007478 (2002-01-01), Tien
Fang Fang, et al., “Automatic Process Migration Of Datapath Hard IP Libraries”, Design Automation Conference, 2004, Proceedings Of The ASP-DAC 2004, Asia and South Pacific Yokohama, Japan Jan. 27-30, 2004, Piscataway, NJ, USA, IEEE, pp. 888-893.
Doan Nghia M.
Icera Inc.
McDermott Will & Emery LLP
LandOfFree
Aligned logic cell grid and interconnect routing architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Aligned logic cell grid and interconnect routing architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Aligned logic cell grid and interconnect routing architecture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3866028