Algorithms for determining path coverages and activity

Details Algorithms for determining path coverages and activity Algorithms for determining path coverages and activity

2002-06-10

2004-06-01

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06745374

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to integrated circuit design, and more particularly, to simulation of a logic circuit design in an integrated circuit.
BACKGROUND OF THE INVENTION
A typical integrated circuit may have a large number of data paths that need to be stored for the purpose of simulating at least a portion of the integrated circuit. A data path in an integrated circuit is referred to as a sequence of leads and gates that create a path from an input node of the logic circuit to an output node of the logic circuit. The data path allows a data value to propagate from the input node to the output of the logic circuit. Unfortunately, the storage and retrieval of the significant number of data paths in the integrated circuit is burdensome. One burden of storing the significant number of data paths is the amount of storage space needed to hold a representation of each of the data paths.
Another burden of storing the significant number of data paths is the time required for looking up and retrieving previously stored data paths. The inability to efficiently store a large number of data paths is a burden to simulating the functional performance of a logic circuit under design. One example of the type of logic fault modeling effected by the inability to efficiently store a large number of data paths is known as Path Delay Fault Modeling. Path Delay Fault Modeling allows an engineer to apply a number of test vectors, a one dimensional array of values, to several input nodes of the logic circuit to determine which of the data paths in the logic circuit fails to propagate a signal transition from an input node to an output node within a specified amount of time. Path Delay Fault Modeling is utilized to simulate logic circuits that do not have scan capability as well as logic circuits that do have scan capability. In logic circuits that do have scan capability, the input node is associated with a first clocked storage element and the output node is associated with a second clocked storage element. The use of Path Delay Fault Modeling requires access to a data structure to store and retrieve the data paths identified as having an amount of delay that requires further analysis by the engineer. Because of the manner in which the data paths are stored, the time needed to retrieve multiple data paths has a linear relationship with the number of data paths to be retrieved. Moreover, because the data paths are not stored in a manner that associates a data path with a functional model or test simulation, it is burdensome for the engineer or program to recall a selected path for evaluation. Consequently, the retrieval of a data path results in a significant computational time burden.
SUMMARY OF THE INVENTION
The present invention addresses the above-described limitations of storing and retrieving data paths of an integrated circuit that have been sensitized by vector simulation. The present invention provides an approach to accelerate the look-up of stored sensitized data paths for use in simulating the functional operation of a selected data path by assigning each identified data path a value. The assigned value provides an indication of how well a particular simulation exercised each of the identified data paths so that an engineer can identify which of the sensitized data paths in the design are candidates for further modeling or simulation.
In one embodiment of the present invention, an apparatus capable of simulating operation of a logic circuit having one or more data paths between one or more input nodes and one or more output nodes provides a method for storing a representation of the logic circuit in a storage device associated with the apparatus. The method provides the steps of identifying each of the data paths in the logic circuit, and assigning an activity value to each of the identified data paths. The assigned activity value indicates the number of times the selected data path propagated a value during a simulation of the logic circuit. The method also provides the steps of creating a representation of the logic circuit based on the identification of each of the data paths and the activity value assigned to each of the data paths. The representation of the logic circuit includes a single occurrence of each of the multiple data paths identified. The method also provides the step of storing the representation of the logic circuit in the storage device.
The apparatus can be instructed to perform the step of determining metrics for the logic circuit based on the identified data paths, the modeling of simulation performed and from the activity values assigned to each identified data path to represent an ability of the simulation to exercise a portion of the logic circuit. The apparatus can also be instructed to apply one or more vectors to one or more input nodes of the logic circuit to identify the data paths that propagate a value for each applied vector and assign an activity factor to the data paths that propagate a value. The activity factor indicates a number of times a selected data path propagated a value for the one or more vectors.
The above described approach benefits an integrated circuit, such as a microprocessor. The assigning of an activity factor or value to each data path and the creation of a representation of the logic circuit that includes a single occurrence of each of the identified data paths significantly reduces the amount of storage needed to store the representation and in the same manner facilitates the retrieval of one or more paths from the representation. The assignment and use of the activity value for each identified data path allows an engineer to recall one or more data paths from a storage device based on the simulation or modeling performed on the logic circuit. In this manner, the engineer can more readily focus a design verification test suite on data paths having design specifications that are critical to the overall operation of the integrated circuit.
In accordance with another aspect of the present invention, an apparatus capable of simulating operation of a logic circuit having one or more data paths between one or more input nodes and one or more output nodes provides a method for creating a data structure that represents at least a portion of the logic circuit. The data structure is held in a storage device associated with the apparatus. The apparatus is instructed to provide the steps of simulating operation of the logic circuit and determining from the simulation which of the one or more data paths is capable of propagating a logic value from an input node to an output node. The method also provides a step of identifying a usage value for each of the one or more data paths capable of propagating the logic value to indicate a number of times the data path propagated the logic value during the simulation operation. The method also provides the step of creating a tree like data structure having a root node for each of the one or more output nodes, and a number of nodes branching from each of the root nodes that represent a discrete data path. The number of nodes branching from each root node equals the number of data paths determined to propagate a logic value from an input node to an output node. The method is also capable of providing steps that determine from the usage value associated with a selected one or more data paths, one or more metric values that represent an ability of a selected simulation or modeling to exercise a portion of the logic circuit.
The above described approach provides the benefit of creating a representation of a logic circuit that can be rapidly traversed while at the same time minimizing an amount of storage needed to store the representation. As such, an engineer is able to use the representation of the circuit to identify data paths having an insufficient amount of activation. The ability to identify data paths with an insufficient amount of activation allows the engineer to target one or more specific data paths having the insufficient amount of activation by d

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