Algorithm to increase logic input width by cascading product...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000

Reexamination Certificate

active

07032203

ABSTRACT:
An algorithm is disclosed to partition input variables between a feeder logic block and a receiver logic block. For a given input variable partition, the algorithm assigns both a cost to the number of product terms cascaded from the feeder logic block to the receiver logic block as well as a cost that increases as the number of input variables assigned to the receiver logic block approaches its maximum input width. The costs for a variety of input variable partitions are tested to determine an optimal input variable partition.

REFERENCES:
patent: 5128871 (1992-07-01), Schmitz
patent: 5357153 (1994-10-01), Chiang et al.
patent: 5969539 (1999-10-01), Veytsman et al.
patent: 6653860 (2003-11-01), Agrawal et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Algorithm to increase logic input width by cascading product... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Algorithm to increase logic input width by cascading product..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Algorithm to increase logic input width by cascading product... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3601089

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.