Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-04-18
2006-04-18
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07032203
ABSTRACT:
An algorithm is disclosed to partition input variables between a feeder logic block and a receiver logic block. For a given input variable partition, the algorithm assigns both a cost to the number of product terms cascaded from the feeder logic block to the receiver logic block as well as a cost that increases as the number of input variables assigned to the receiver logic block approaches its maximum input width. The costs for a variety of input variable partitions are tested to determine an optimal input variable partition.
REFERENCES:
patent: 5128871 (1992-07-01), Schmitz
patent: 5357153 (1994-10-01), Chiang et al.
patent: 5969539 (1999-10-01), Veytsman et al.
patent: 6653860 (2003-11-01), Agrawal et al.
Bosco Gilles
Xue Hua
Bowers Brandon
Hallman Jonathan W.
Lattice Semiconductor Corporation
MacPherson Kwok Chen & Heid
Siek Vuthe
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