Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-07-29
2008-07-29
Portka, Gary J (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S202000, C711S203000
Reexamination Certificate
active
07406567
ABSTRACT:
A system and method for improving the speed of packet switching in a routing platform that maps shared I/O memory into two address spaces. The first address space is mapped with the cache attribute and uses the cache write through attribute. Addresses in this address space are not equal to the physical address in the shared I/O memory and are translated to the physical addresses. Code executed by the CPU to switch packets utilizes the first address space to access packet data. The second address space is mapped with the non-cache attribute and addresses in this space are equal to the physical addresses in the shared I/O memory. The second address space is utilized by I/O devices when accessing shared I/O memory. Addresses of buffers for storing packet data in the shared I/O memory are converted from the first address space to the second address space when given to I/O devices.
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Ajay Hampapur
Kumar Nipa
Manian Radesh
Nakil Harshad
Reddy Rajashekar
Choe Yong J.
Cisco Technology Inc.
Krueger Charles E.
Portka Gary J
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