Algorithm for full-chip resistance extraction

Details Algorithm for full-chip resistance extraction Algorithm for full-chip resistance extraction

2006-06-27

2006-06-27

Pert, Evan (Department: 2826)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C703S014000

Reexamination Certificate

active

07069527

ABSTRACT:
A method to convert a wire layout geometry to a filament topology for determination of chip resistance is provided. The method includes resolving overlap of layout segments of the wire layout geometry and inserting a vertical filament into each of the layout segments. The method further includes connecting vertical filaments using lateral connections and merging connected parallel filaments. The method also includes removing open filaments and modifying the filament structure in a bend region based on relative dimensions of the vertical filaments within the bend region.

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patent: 2004/0225485 (2004-11-01), Lowther et al.
patent: 2004/0225975 (2004-11-01), Pramono

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