Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-04
2003-04-29
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S016000, C703S017000, C703S028000
Reexamination Certificate
active
06557149
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the areas of digital circuits and digital logic. In particular, the present invention provides a method and system for determining vectors to stimulate all paths and arcs through an LVS (“Low Voltage Differential Sense”) circuit.
BACKGROUND INFORMATION
LVS circuits are being developed as a means to decrease circuit area, increase throughput and consume less power than other circuit families. LVS circuits utilize large networks of precharged dual rail gates with low voltage outputs and sense amplifiers to restore the output to full rail signals.
LVS is implemented using pass-gate technology where only n-type gates are used to pass logic values in a source-follower configuration.
FIG. 1A
illustrates a topology of an LVS gate according to one embodiment of the present invention. Note that the topology depicted in
FIG. 1A
is merely exemplary and is not intended to limit the scope of the present invention. Referring to
FIG. 1A
, note that the logic utilizes a dual-rail protocol (
105
a
,
105
b
) where a pair of wires encode data values of one and zero. The idle state is encoded with both wires reset. A logic one or zero is physically represented with one wire pulled high and the other low. Latching circuit
110
, which is controlled by domino clock
115
is coupled to DCN (“Diffusion Connected Network”) via rails
105
a
and
105
b
. Reset of DCN
120
is controlled via reset clock. The dual-wire pair
105
a
,
105
b
is coupled to sense amplifier (“SA”)
130
, which can detect and latch very small differentials between wire pairs
105
a
and
105
b
. SA
130
is clocked via sense amplifier clock
135
and is further coupled to CDL (“Clocked Differential Logic”) block
140
, the output of which may be used to drive other LVS gates.
FIG. 1B
depicts a block schematic for an LVS circuit according to one embodiment of the present invention. As shown in
FIG. 1B
, DCN network
120
includes function (F)
160
a
and function complement (F′) networks
160
b
, which each respectively feed an input of SA
130
. Each network
160
a
includes transistors functioning as drive transistors
170
, pass transistors
180
and reset transistors
190
.
LVS gates offer significant advantages over static or domino logic for particular topologies and logic functions, particular AND and MUX operations. In particular, significant amounts of logic can be placed in the pass-gate network (DCN
120
), which is equivalent to several stages of static or domino logic that would be required to implement the same function. Therefore, the overhead of sense amplifiers can be compensated by the decreased single-stage latency of the pass-gate function. The ability to push complex logic in the pass gate chain also significantly minimizes area when compared with other implementations. Further, LVS technology offers the advantage that it can run at double clock frequency since an LVS pipeline includes fewer logic levels than standard clocked pipelines (clocked FF/CDL, pass gate chain, p-SA, n-CDL). In addition, LVS circuits consume less power due to the reduced size of the transistors.
FIGS. 2A-2B
illustrate a number of CMOS (“Complementary Metal Oxide Semiconductor”) gates and exemplary LVS counterparts according to one embodiment of the present invention. In particular,
FIG. 2A
compares the topology for an inverter implemented using CMOS technology
205
and the DCN
120
of an inverter implemented using LVS technology
210
. Note, in particular, the dual rail topology of the inverter using LVS technology
210
. That is, dual rail inputs &agr; and {overscore (&agr;)} are cross-coupled to respective outputs z and {overscore (z)}.
FIG. 2B
compares the topology for an exclusive or (“XOR”) gate implemented using CMOS technology and using LVS technology.
The topology of LVS circuits present novel challenges for performing simulation and timing analysis, which are not tractable by standard timing and analysis tools directed toward typical static or dynamic gates (e.g., CMOS or domino gates). The pass-gate networks in current implementations may run from tens of transistors per DCN to thousands of transistors. Each of the DCNs can be viewed as a single very complex gate. While these gates have a single DCN like other standard logic gates (e.g., AND gates), they differ in complexity because these networks can be comprised of hundreds of inputs and outputs and thousands of transistors.
The clocking of an LVS block is also more complex than other logic families such as domino logic. LVS blocks can have multiple pulsed clocks. These circuits typically operate in a mode where many of the inputs are designed to switch simultaneously and this effect can have a significant impact on the delay through the DCN due to Miller capacitance. Skew between the arrival time of input levels can also significantly change the delay through the pass-gate network since skew differences can alter the charge steering routes through the DCN.
Furthermore, a single arc from an input to a sense amplifier can be enabled by one or more valid input vectors. Typically, all possible vectors must be found to enable all arcs and paths through an LVS block. Many of these arcs are subsets of other arcs. The complexity of vectors can grow exponentially but may be bounded by O(n
2
).
The custom nature of LVS circuits coupled with their size, clocking complexity and dual-rail differential signal sensing result in a circuit class that is unsupported by standard timing tools. Correctly validating the timing of LVS circuits is critical to efficient production. In particular, the following criteria are necessary for accurate analysis of LVS circuits:
1) Timing validation tools that require little designer intervention;
2) Accurate characterization;
3) Validation of the timing of an LVS block as a function of arrival times and variations in clocks and input signals;
4) A timing model that can be used by higher level timing tools. An LVS block has high impedance inputs and full-swing outputs that support higher level timing analysis (e.g., PathMill black boxes);
5) Reporting structure that indicates slacks and vectors to exercise the circuit for these slacks so that the designer can improve the circuit and repair any violations;
6) Cross-platform compatibility.
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Morrise Matthew C.
Stevens Kenneth S.
Intel Corporation
Kik Phallaka
Smith Matthew
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