Algorithm and methodology for the polygonalization of sparse...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06904571

ABSTRACT:
An method of creating a physical layout of an integrated circuit. A schematic file (600) is mapped directly to a physical layout using the location of elements and routing of interconnections as specified in the schematic file (600). The method takes advantage of constraints on the schematic design to provide the layout file (675) quickly, without complex routing programs. Design rules violations are anticipated and corrected in some cases. In other cases, the design rule violations are annotated, if the designer intentionally placed them in the design.

REFERENCES:
patent: 5051938 (1991-09-01), Hyduke
patent: 5097422 (1992-03-01), Corbin et al.
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5231590 (1993-07-01), Kumar et al.
patent: 5381343 (1995-01-01), Bamji
patent: 5402357 (1995-03-01), Schaefer et al.
patent: 5452224 (1995-09-01), Smith, Jr. et al.
patent: 5459673 (1995-10-01), Carmean et al.
patent: 5461579 (1995-10-01), Misheloff et al.
patent: 5463563 (1995-10-01), Bair et al.
patent: 5490095 (1996-02-01), Shimada et al.
patent: 5604680 (1997-02-01), Bamji
patent: 5798937 (1998-08-01), Bracha et al.
patent: 5822214 (1998-10-01), Rostoker
Altera Corp., “Max + Plus II, Programmable Logic Development System & Software,” Data Book, Mar. 1995, Version 6, pp. 511-531.
Altera Corp. “EDA Software Support,” Data Book 1995, pp. 549-561.
Xilinx Corp., “Development Systems,” The Programmable Logic Data Book, 1994, pp. 7-1 to 7-38.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Algorithm and methodology for the polygonalization of sparse... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Algorithm and methodology for the polygonalization of sparse..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Algorithm and methodology for the polygonalization of sparse... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3484012

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.