Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-07-09
2002-10-22
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S688000, C438S627000, C438S643000, C438S653000, C438S669000
Reexamination Certificate
active
06468908
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field Of The Invention
This invention relates to a method of fabrication for metal wiring used in semiconductor integrated circuit devices, and more specifically, to an aluminum copper alloy sputtering method, whereby the sputtered metal is rapidly cooled down by a post-metal quenching process, to prevent deleterious CuAl
2
precipitation.
(2) Description Of Related Art
As an introduction and background to Prior Art, the conventional processing schemes for Al—Cu, Al—Cu—Si and related alloys and compounds used in combination with TiN anti-reflection coatings (ARC) or metal barriers, describe various wiring deposition heating and cooling treatments, e.g., pre-cooling of wafers, cooling during deposition and controlled cooling after deposition, to prevent deleterious effects, i.e., silicon precipitation and TiN/Al film stress effects.
Related Prior Art background patents will now be described in this section.
U.S. Pat. No. 5,843,842 entitled “Method for Manufacturing a Semiconductor Device Having a Wiring Layer Without Producing Silicon Precipitates” granted Dec. 1, 1998 to Lee et al. teaches various heat treatment processes to avoid silicon precipitates and aluminum spiking in a conducting wiring layers. The first metal layer is an Al—Si or Al-Cu-Si alloy not more than one quarter of a predetermined thickness of the wiring layer, and the second metal layer is pure Al, or alloys of Al—Ti or Al—Cu. These layers are deposited at low temperature, below 150° C. The wiring layer is heat-treated at various times and temperatures to avoid deleterious effects in the wiring layer.
U.S. Pat. No. 5,918,149 entitled “Deposition of a Conductor in a Via Hole or Trench” granted Jun. 29, 1999 to Besser et al. teaches various TiN/Al sputtering, physical vapor deposition (PVD), and titanium chemical vapor deposition (CVD) process recipes. After a three step Al or alloy sputtering deposition process, with high, then low power and then high power again, the wafer is cooled and polished. The barrier layer is formed of titanium type compounds, e.g., titanium nitride, titanium oxynitride, titanium carbonitride, or titanium silicide.
U.S. Pat. No. 5,994,219 entitled “Add One Process Step to Control the Si Distribution of AlSiCu to Improved Metal Residue Process Window” granted Nov. 30, 1999 to Lin et al. teaches an AlSiCu alloy wiring process with a TiN barrier. Claimed is a pre-metal cooling step with wafer immersion for 30 seconds to cool the wafer to about 11 ° C., just prior to the metal process. Cooling before the AlSiCu deposition step, resulted in low metal residue for wiring formation.
U.S. Pat. No. 5,930,673 entitled “Method for Forming a Metal Contact” granted Jul. 27, 1999 to Chen et al. describes a method of fabricating an aluminum metal contact and controlled, relative low deposition rate, ramping both deposition rate and temperature during the deposition, which results in the device being heated from cooler temperatures within the chamber. The method tends to deposit aluminum in contact vias without void formation.
U.S. Pat. No. 5,994,217 entitled “Post Metallization Stress Relief Annealing Heat Treatment for ARC TiN Over Aluminum Layers” granted Nov. 30, 1999 to Ng describes a method of fabricating a low stress, anti-reflective coating (ARC) of TiN, which is over Al/Cu/Si sputtered layers. A post metallization, three step heat treatment is performed on the layers of sputtered metal layers and the ARC TiN top layer. First, a controlled temperature ramp up step is performed. Second a temperature hold step is performed at 450° C. for about 30 seconds. Third, a ramp down in temperature is performed at a controlled rate. This heat treatment described reduces the stress between the ARC TiN and Al layers.
U.S. Pat. No. 5,814,556 entitled “Method of Filling a Contact Hole in a Semiconductor Substrate with a Metal” granted Sep. 29, 1998 to Wee et al. discloses a method of filling with aluminum or aluminum alloy, a high aspect-ratio contact hole. Backside wafer cooling of the semiconductor wafer substrate is performed prior to and during the deposition of the aluminum or aluminum alloy film, in film deposition temperatures in the range between −25° C. and room temperature. A non-contact type gas conduction method is used for lowing the deposition temperature, by using, e.g., liquid nitrogen, helium (He) and cooling water.
SUMMARY OF THE INVENTION
This invention relates to a method of fabrication for metal wiring used in semiconductor integrated circuit devices, and more specifically, to an aluminum copper alloy sputtering method, whereby the sputtered metal is rapidly cooled down by a post-metal quenching process, to prevent deleterious CuAl
2
precipitation.
The main embodiments of the present invention are the formation of a TiN sputtered bottom barrier layer followed by a sputtered Al—Cu wiring layer with an in situ post-metal quench (key step), followed by a second TiN top barrier layer. The key processing step is the post-metal quench after sputter deposition of the Al—Cu wiring layer, to prevent CuAl
2
precipitation. The CuAl
2
precipitates, if allowed to form, can result in deleterious residues in the wiring lines after wiring line patterning and etching. Furthermore, these residues block the etchant removal of the underlying bottom TiN layer, and in effect cause electrical shorts, especially between closely spaced wiring lines.
Several manifestations of the key aspects of the present invention follow, all to achieve a post-metal quench or very rapid cool down step, after sputtered Al—Cu wiring deposition. Basically, insert an in situ, one-step cool down step between the Al—Cu deposition and the second TiN deposition to quench the wafer temperature. Alternately, use another AlCu chamber in a cluster tool to achieve in situ cooling by setting the chamber heater to room temperature. Practically and most effective is to employ an in situ cool down recipe in the Al—Cu deposition chamber, where the wiring layer is deposited, and rapidly quench the wafer after sputter deposition by backside wafer cooling with low temperature helium gas or argon gas. Note, all the “standard” deposition processes and tool recipes for the TiN barrier, Al—Cu wiring, and top TiN barrier remain the same. Thus, the post-metal quench solves the CuAl
2
precipitate problem directly, without the need for addition process and recipe changes.
By not requiring addition processing changes, in the related sputter deposition processing steps of bottom TiN barrier, Al—Cu wiring, and top TiN barrier layer, the desirable optimum deposition conditions for step coverage and high aspect ratio contacts, can be achieved for surface mobility and flow without compromising these layers or recipes. Furthermore, no additional changes were required in patterning and etching of the metal wiring lines. Therefore, the post-metal quench method solves the deleterious effects and assures the integrity of the metal wiring, shown in the invention's specifications.
This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the “DESCRIPTION OF THE PREFERRED EMBODIMENTS” section.
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patent: 5656543 (1997-08-01), Chung
patent: 5814556 (1998-09-01), Wee et al.
patent: 5843842 (1998-12-01), Lee et al.
patent: 5918149 (1999-06-01), Besser et al.
patent: 5930673 (1999-07-01), Chen et al.
patent: 5994217 (1999-11-01), Ng
patent: 5994219 (1999-11-01), Lin et al.
patent: 6103630 (2000-08-01), Lee et al.
patent: 6159839 (2000-12-01), Jeng et al.
patent: 6235633 (2001-05-01), Jang
Chen Cheng-Shien
Chen Li-Der
Lin Chih-Ching
Liu Chung
Wen Chih-Min
Ackerman Stephen B.
Nguyen Thanh
Nguyen Tuan H.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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