Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-01-09
2008-08-26
Everhart, Caridad M (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S682000, C438S664000, C257SE21165, C257SE21166, C257S755000
Reexamination Certificate
active
07417290
ABSTRACT:
Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance. Additionally, the method allows such a tensile silicide region to be formed using a relatively thin first metal layer-protective cap layer-second metal layer stack, and particularly, a relatively thin second metal layer, to minimize mechanical energy build up at the junctions between the gate conductor and the sidewall spacers to avoid silicon bridging.
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PCT International Search Report (Form PCT/ISA/220), dated May 4, 2007, for International Application No. PCT/EP2007/050175, 5 pages.
U.S. Appl. No. 10/905,949, filed Jan. 27, 2005, entitled “Silicide Cap Structure and Process for Reduced Stress and Improved Gate Sheet Resistance”.
Hon Wong Keith Kwong
Purtell Robert J.
Abate, Esq. Joseph
Everhart Caridad M
Gibb & Rahman, LLC
International Business Machines - Corporation
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