Aggregate sensitivity for statistical static timing analysis

Details Aggregate sensitivity for statistical static timing analysis Aggregate sensitivity for statistical static timing analysis

2006-06-12

2008-11-25

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C703S002000, C703S013000, C703S014000

Reexamination Certificate

active

07458049

ABSTRACT:
A system and a method are disclosed for circuit analysis. A circuit modeling system calculates sensitivities of gates for statistical static timing analysis of a circuit. Timing distribution sensitivities of gates and correlations between the sensitivities are determined. A Monte Carlo simulation is run using the sensitivities to determine timing distribution of paths and determine probabilities of paths being the critical path. Aggregate sensitivities for cells are also determined.

REFERENCES:
patent: 7293248 (2007-11-01), Chang et al.
patent: 2006/0059446 (2006-03-01), Chen et al.
Jess, J.A.G. et al., “Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits,” Design Automation Conference, Anaheim, CA, 2003, pp. 932-937.
Naidu, S.R., “Tuning for Yield—Towards Predictable Deep-Submicron Manufacturing,” Ph.D. Thesis, Department of Electrical Engineering, Eindhoven University of Technology, The Netherlands, Jul. 13, 2004, 197 pages.

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