Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2001-06-12
2003-02-11
Talbott, David L. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S256000, C361S723000, C361S813000, C257S677000, C428S209000
Reexamination Certificate
active
06518508
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a lead frame for a semiconductor package, and more particularly, to a lead frame for a semiconductor package which can maintain a high quality of the package under a high-temperature environment even if a plating layer is thin, can prevent migration of silver (Ag) due to a reduction in the thickness of an Ag-plated layer, and can reduce the manufacturing cost.
2. Description of the Related Art
A semiconductor lead frame basically includes a die pad unit for mounting a semiconductor memory chip and fixing the same at a static state, an inner lead connected to the chip by wire bonding, and an outer lead for connection with an external circuit. The wire-bonded chip and the wire-bonded inner lead are hermetically sealed by a molding compound to form a semiconductor package. The semiconductor lead frame having the aforementioned configuration is generally manufactured by a stamping process or an etching process.
In such a lead frame for a semiconductor package, in order to maintain good wire bondability in an inner lead and good adhesion between a pad and a chip, a metal material such as silver (Ag) is plated on the pad and the tip of the inner lead of the lead frame. Also, after resin passivation film molding, in order to improve solderability during mounting an outer lead connected to an external circuit board, solder plating, that is, tin-lead (Sn-Pb) plating, is performed on a predetermined region of the outer lead. However, since the plating is generally performed in a wet process after resin passivation film molding, a Sn—Pb plating solution soaks through a gap between epoxy and lead, which degrades the reliability of completed products. In order to solve this problem, a pre plating method (pre plated frame) has been proposed. In the pre plated frames, prior to semiconductor packaging, a metal having excellent wire bondability, chip adhesion and solder wettability is pre plated on a metal material, thereby omitting a lead plating step during a semiconductor post packaging process. Thus, since use of the pre plated lead frames simplifies the semiconductor post packaging process and environmental contamination due to lead plating can be reduced, much attention has recently been paid to the pre plated frames.
Considering that a semiconductor assembling process including semiconductor chip adhesion, wire bonding, epoxy molding, soldering and the like, is generally performed at a high temperature of 200° C. or higher, the kind of an outer plating layer is quite an important factor in manufacturing a lead frame by a preplating method. Requirements for an outer plating layer of a lead frame manufactured by a pre plating method include oxidation resistance at a higher temperature, good bondability with a bonded wire used in wire bonding, good adhesion with a chip, generally made of silicon, good moldability with an epoxy resin which is a molding material, good fusibility with lead during soldering. In addition, in order to prevent abrasion of a bonding capillary during wire bonding, the outer plating layer should be made of metal having adequate ductility. The long-term reliability of a semiconductor device must be ensured, without short-circuiting due to diffusion of plated metal in the outer layer into a medium in contact therewith under hot and humid conditions for a long period of time, which is so-called “migration.” The outer plating layer material satisfying the requirements is a noble metal such as palladium (Pd), gold (Au) or silver (Ag). Specifically, Au and Ag have been conventionally preferred due to their excellent conductivity and ductility. In the case of using Au, 0.5 to 2 &mgr;m thick Au is preferably plated. In the case of using Ag, 1 to 5 &mgr;m thick Ag is preferably plated. However, as a semiconductor package has recently been miniaturized and highly integrated, Pd, which has a denser structure and which does not cause migration, has gained more attention as an outer plating layer material than Au or Ag causing migration.
However, in the case of plating the noble metal, in order to maintain flatness of a plating layer and to reduce the amount of a noble metal used, an underlying plating layer made of a metal having a good plating adhesion strength to the material to be plated thereon, is first formed and noble metal plating is then performed on the underlying plating layer. Here, nickel (Ni) is widely used as a material of the underlaying plating layer.
FIGS. 1 through 4
show the structure of a plating layer of a conventional semiconductor lead frame based on a pre plated method.
First,
FIG. 1
shows a cross-section of a conventional semiconductor lead frame disclosed in Japanese Patent No. 1,501,723, directed to a lead frame for a plastic package in which a Ni underlying plating layer
12
is formed on a chip mount section and a lead frame surface
11
of a wire bonding section, and a plating layer
13
made of a Pd or Pd alloy is formed as an outer layer. In one embodiment of this patent, 0.1 to 1 &mgr;m thick Pd plated layer is formed on Ni plated layer, 0.1 to 1 &mgr;m thick. According to this patent, in the case of thickly plating Au or Ag as the outer layer (Au: 0.5 to 2 &mgr;m; Ag: 1 to 5 &mgr;m), the migration problem can be prevented.
Pd has a very dense structure and is a very hard metal. Further, when the outer layer is made of Pd, it is likely to be oxidized in the course of a high temperature semiconductor packaging process. Thus, the plating layer gets harder and the melting point thereof gets higher, thereby lowering solderability and causing wearing or damage of a wire bonding capillary. Also, since Pd is a metal having a hydrogen embrittlement, it is combined with hydrogen when exposed to the atmosphere, resulting in brittleness of the plating layer.
FIG. 2
shows a cross section of a conventional semiconductor lead frame disclosed in Japanese Patent No. 2,543,619, which is proposed for overcoming the problems with the structure disclosed in Japanese Patent No. 1,501,723, and in which there is provided a lead frame for a semiconductor device having a plurality of metal coated layers on a copper (Cu) or Cu alloy layer, wherein a Ni underlying plating layer
22
is disposed on the Cu or Cu alloy layer
21
, a 0.3 &mgr;m or less thick Pd or Pd alloy layer is
23
is entirely formed thereon and 0.001 to 0.1 &mgr;m thick Au plated layer
24
is formed on the Pd or Pd alloy layer on an outer lead of the lead frame.
However, in the case where the semiconductor lead frame having the stacked structure shown in
FIG. 2
is applied to a semiconductor package requiring high reliability, the following problems may occur. First, a lead frame having an Au plated layer as the outer plating layer is comparatively weaker than the lead frame having an Ag outer plating layer in view of adhesion of a wire bonding portion, so that cracks are generated at the wire bonding portion after packaging the semiconductor device, causing product defects such as short-circuiting. This is due to repeated thermal shock applied to a lead frame having relatively weaker molding adhesion, causing repetition of feeble fluctuation between the mold portion and a lead frame bonding surface and generating fatigue therefrom. Further, the cracks generated due to fatigue may result in short-circuiting. As described above, repetition of contraction and expansion, due to repeated thermal stress, generates cracks at the interface between a mold and a lead frame or cutting of a wire bonding portion, which is called a “heel crack.” Crack resistance tests were carried out for the lead frame having the above-described structure, and the results thereof showed that cracks were generated at 600 TC. cycles or below, as will be described in Comparative Example 1, which is very poor compared to the crack resistance in the case of using Ag as the outer plating layer, in which cracks were generated at over 1000 TC. cycles. Thus, the semiconductor product having the aforementioned structure has a problem in attaining l
Kim Nam-seog
Park Se-Chul
Patel I B
Samsung Techwin Co. Ltd.
St. Onge Steward Johnston & Reens LLC
Talbott David L.
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