Advanced transistor structures with optimum short channel contro

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257366, 257372, 257373, 257901, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

056082533

ABSTRACT:
A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.

REFERENCES:
patent: 4864377 (1989-09-01), Widdershoven
patent: 5191401 (1993-03-01), Shirai et al.
patent: 5247200 (1993-09-01), Momose et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Advanced transistor structures with optimum short channel contro does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Advanced transistor structures with optimum short channel contro, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Advanced transistor structures with optimum short channel contro will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2148076

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.