Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2004-08-31
2008-12-16
Patel, Niketa I. (Department: 2184)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C709S233000, C709S251000
Reexamination Certificate
active
07467243
ABSTRACT:
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
REFERENCES:
patent: 6584101 (2003-06-01), Hagglund et al.
patent: 6594701 (2003-07-01), Forin
patent: 6668308 (2003-12-01), Barroso et al.
patent: 7209996 (2007-04-01), Kohn et al.
patent: 2003/0204636 (2003-10-01), Greenblat et al.
patent: 2005/0080953 (2005-04-01), Oner et al.
Alpha 21264 Microprocessor Product Brief; Sep. 9, 1998; Digital Equipment Corporation; Preliminary Edition; p. 1; http://ftp.digital.com/pub/digital/info/semiconductor/literature/21264pb.pdf.
Final Office Action Summary from U.S. Appl. No. 10/930,187, mailed on May 13, 2008.
Office Action Summary from U.S. Appl. No. 10/930,937, mailed on Apr. 30, 2008.
Office Action Summary from U.S. Appl. No. 10/931,014, mailed on May 13, 2008.
Office Action Summary from U.S. Appl. No. 10/930,179, mailed on May 12, 2008.
Office Action Summary from U.S. Appl. No. 10/930,456, mailed on Mar. 14, 2008.
Office Action Summary from U.S. Appl. No. 10/930,939, mailed on May 6, 2008.
Office Action Summary from U.S. Appl. No. 10/931,003, mailed on Jan. 24, 2008.
Final Office Action Summary from U.S. Appl. No. 10/931,003 mailed on Jul. 24, 2008.
Office Action Summary from U.S. Appl. No. 10/930,456 mailed on Sep. 3, 2008.
Final Office Action Summary from U.S. Appl. No. 10/930,938 mailed on Sep. 3, 2008.
Notice of Allowance from U.S. Appl. No. 10/930,179 mailed on Sep. 11, 2008.
Final Office Action Summary from U.S. Appl. No. 10/930,455 which was mailed on Oct. 3, 2008.
Hass David T.
Rashid Abbas
Patel Niketa I.
RMI Corporation
Roche John B
Zilka-Kotab, PC
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