Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2004-07-23
2009-12-01
Thomas, Shane M (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S141000, C709S251000
Reexamination Certificate
active
07627721
ABSTRACT:
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
REFERENCES:
patent: 6182210 (2001-01-01), Akkary et al.
patent: 6341337 (2002-01-01), Pong
patent: 6507862 (2003-01-01), Joy et al.
patent: 6574725 (2003-06-01), Kranich et al.
patent: 6629268 (2003-09-01), Arimilli et al.
patent: 6668308 (2003-12-01), Barroso et al.
patent: 6725334 (2004-04-01), Barroso et al.
patent: 6981079 (2005-12-01), Dawkins et al.
patent: 7000048 (2006-02-01), McAlpine et al.
patent: 7082519 (2006-07-01), Kelsey et al.
patent: 7181742 (2007-02-01), Hooper
patent: 2002/0046324 (2002-04-01), Barroso et al.
patent: 2002/0095562 (2002-07-01), Nakanishi et al.
patent: 2002/0147889 (2002-10-01), Kruckemyer et al.
patent: 2003/0009626 (2003-01-01), Gruner et al.
patent: 2003/0041173 (2003-02-01), Hoyle
patent: 2003/0088610 (2003-05-01), Kohn et al.
patent: 2003/0120876 (2003-06-01), Hass et al.
patent: 2003/0154352 (2003-08-01), Jamil et al.
patent: 2003/0208521 (2003-11-01), Brenner et al.
patent: 2003/0212830 (2003-11-01), Greenblat et al.
patent: 2003/0217237 (2003-11-01), Benveniste et al.
patent: 2003/0231645 (2003-12-01), Chandra et al.
patent: 2004/0128401 (2004-07-01), Fallon et al.
patent: 2004/0230752 (2004-11-01), Blake et al.
Hennessy and Patterson, “Computer Architecture: A Quantitative Approach,” Morgan Kaufmann Publishers, Inc., pp. 654-662, 1996.
“Microsoft Computer Dictionary,” Fifth Edition, Microsoft Press, 2002, pp. 505.
“IEEE 100—The Authoritative Dictionary of IEEE Standards Terms,” Seventh Edition, IEEE Press, 2000, pp. 716.
Chakraborty: “System-Level Timing Analysis and Scheduling for Embedded Packet Processors”. PhD Thesis, Computer Engineering and Networks Laboratory, ETH Zurich, Switzerland, Apr. 2003, Pertinent pp. 1, 3-6, 15-30, 41-56, 66-67.
Fiske et al. “Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors”. Appears in: Proceedings of the First International Symposium on HPCA, Jan. 1995, Pertinent pp. 1-6.
Pappu et al. “Scheduling Processing Resources in Programmable Routers”. Infocom 2002. Twenty-First Annual Joint Conference of the IEEE Computer and Communications Societies. Proceedings. IEEE vol. 1, 23-27, Jun. 2002, Pertinent pp. 1-5.
Wolf et al. “Locality-Aware Predictive Scheduling of Network Processors”. Performance Analysis of Systems and Software, 2001. ISPASS. 2001 IEEE International Symposium on Nov. 4-6, 2001, Pertinent pp. 1-4.
Hennessy and Patterson, “Computer Architecture: A Quantitative Approach,” Morgan Kaufmann Publishers, Inc., pp. 654-662, 1996.
“Microsoft Computer Dictionary,” Fifth Edition, Microsoft Press, 2002, pp. 505.
“IEEE 100-The Authoritative Dictionary of IEEE Standards Terms,” Seventh Edition, IEEE Press, 2000, pp. 716.
RMI Corporation
Thomas Shane M
Zilka-Kotab, PC
LandOfFree
Advanced processor with cache coherency does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Advanced processor with cache coherency, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Advanced processor with cache coherency will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4076047