Advanced processor translation lookaside buffer management...

Details Advanced processor translation lookaside buffer management... Advanced processor translation lookaside buffer management...

2008-03-18

2008-03-18

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

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C711S163000, C711S152000

Reexamination Certificate

active

10898150

ABSTRACT:
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

REFERENCES:
patent: 5940872 (1999-08-01), Hammond et al.
patent: 6668308 (2003-12-01), Barroso et al.
patent: 2002/0069328 (2002-06-01), Chauvel
patent: 2003/0041173 (2003-02-01), Hoyle
patent: 2003/0088610 (2003-05-01), Kohn et al.
patent: 2003/0101322 (2003-05-01), Gardner
patent: 2003/0212830 (2003-11-01), Greenblat et al.

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