Advanced memory device having reduced power and improved...

Details Advanced memory device having reduced power and improved... Advanced memory device having reduced power and improved...

2011-05-24

2011-05-24

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100

Reexamination Certificate

active

07948817

ABSTRACT:
A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.

REFERENCES:
patent: 6212127 (2001-04-01), Funaba et al.
patent: 6980042 (2005-12-01), LaBerge
patent: 2003/0067332 (2003-04-01), Mikhalev et al.

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