Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-01-14
2002-04-02
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S683000, C438S656000, C438S664000, C438S711000
Reexamination Certificate
active
06365516
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to a method of fabricating a cobalt silicide film on a substrate.
2. Description of the Related Art
A typical field effect transistor implemented in silicon consists of a source and a drain formed in a silicon substrate, and separated laterally to define a channel region in the substrate. A gate electrode composed of a conducting material, such as aluminum or polysilicon, is disposed over the channel region and designed to generate an electric field in the channel region. Changes in the electric field generated by the gate electrode enable, or alternatively, disable the flow of current between the source and the drain.
In a conventional process flow for forming a typical field effect transistor, a gate oxide layer is grown on a lightly doped silicon substrate and a layer of polysilicon is deposited on the gate oxide layer. The polysilicon and the gate oxide are then anisotropically etched back to the upper surface of the substrate leaving a polysilicon gate electrode stacked on top of a gate oxide layer. Following formation of the polysilicon gate electrode, a source and a drain are formed by implanting a dopant species into the substrate. The substrate is annealed to activate the dopant in the source and the drain. Dielectric sidewall spacers are frequently formed adjacent to the gate electrode to serve as implant masks and barriers to hot carriers.
The interfaces between structures of a transistor implemented in silicon or polysilicon, such as source/drain regions and poly gates, and local or global interconnects typically exhibit relatively high series sheet resistances. The resistances can lead to undesirably high power consumption and heat propagation in integrated circuits. One method in use for years to reduce the series resistance of these types of structural interfaces involves the fabrication of metal-silicide layers on sources and drains, and on gate electrodes where polysilicon is the material of choice. Self-aligned silicidation (“salicidation”) is perhaps the most common application of this method.
In conventional salicidation, a metal capable of reacting with silicon, such as titanium, is deposited on the gate, the sidewall spacers, and the source and drain regions. A one or two step anneal is performed to react the titanium with the polysilicon of the gate and the silicon of the source and drain regions to form TiSi
2
. Following the anneal, an etch is performed to remove any unreacted titanium.
In addition to serving as implant masks, one of the principal functions of sidewall spacers is to separate the silicided gate from the source/drain regions. Despite the incorporation of spacers, silicide may form laterally and easily bridge the separation between the polysilicon gate electrode and the silicon source/drain regions causing the gate to become shorted to the source/drain regions. This so-called “bridging effect” occurs where silicon diffuses into the titanium regions that cover the sidewall spacers and subsequently reacts with the titanium.
Certain conditions tend to favor lateral TiSi
2
formation. Conventional furnace annealing in an inert gas atmosphere (e.g., argon for approximately 30 minutes) may foster rapid lateral TiSi
2
formation. Processing in the sub-0.25 &mgr;m domain also appears to raise the frequency of lateral silicide formation. In sub-0.25 &mgr;m processing, the minimum gate width may approach or even reach the dimensions of the grain boundaries between the individual grains of the polycrystalline silicon gate electrode. As the minimum device size approaches the dimensions of the grain boundaries in the polysilicon, the rate of silicon diffusion from the polysilicon into the titanium increases. The increased diffusivity is believed to stem from the elimination of pluralities of intersecting polysilicon grain boundaries that are present in larger scale processes. These grain boundaries act as natural barriers to silicon diffusion.
Cobalt silicide processing has gained some recognition as a potential replacement for TiSi
2
in salicidation processing. Cobalt silicide provides acceptable values of sheet resistance and presents much lower risk of bridging. However, conventional CoSi
2
processing is not without disadvantages. Most conventional methods are similar to conventional TiSi
2
processing in that a layer of cobalt is deposited on silicon and/or polysilicon and annealed to trigger conversion to cobalt silicide. However, in contrast to titanium silicide processing, cobalt silicide fabrication is much more sensitive to the presence of oxide films present on monocrystalline silicon and polysilicon surfaces. Such insulating films can interfere with the cobalt-silicon reaction and lead to variations in cobalt silicide film thickness or a complete absence of cobalt silicide in certain areas. The sensitivity of the cobalt-silicon reaction to the presence of underlying insulating films, particularly oxide films, is due to the inability of cobalt to reduce oxide during the silicide-forming anneals. Titanium can readily reduce such films.
Insulating films on exposed silicon and polysilicon surfaces can form from a variety of mechanisms. For example, native oxides with thicknesses of 25 to 50 Å quickly form on silicon by simply exposing a wafer to air. Silicon surfaces may also collect carbon from derelict carbon dioxide present in processing chambers or from ambient carbon dioxide outside of such chambers. In one conventional process, the native oxide problem is addressed by chemically cleansing exposed silicon and polysilicon surfaces. A wafer is initially subjected to ammonium hydroxide-peroxide-water and sulphuric acid-peroxide-water cleansing steps. A wet HF dip is then performed to remove as much native oxide as possible. The difficulty with this approach is the potential for the HF dip to leave oxide in various places on the wafer.
Another conventional cleaning process for the removal of native oxides involves the use of sputter etching. For example, a process utilized by Digital Equipment Corporation in 1996 employed an argon ion sputter etch with an induced bias applied to the wafer of about 275 volts. The efficacy of some conventional sputter etch cleaning processes has been debated. At least one author has argued that some conventional sputter etching processes used as means of removing native oxides may cause contamination of the sputtered wafer surfaces due to the redeposition of backsputtered material.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a method of fabricating a circuit structure on a silicon surface is provided that includes exposing the silicon surface to a plasma ambient containing hydrogen and an inert gas, and depositing a metallic material capable of forming silicide on the silicon surface. The metallic material is heated to form a metal silicide on the silicon surface.
In accordance with another aspect of the present invention, a method of fabricating a silicide structure on a silicon surface of a substrate is provided that includes exposing the silicon surface to a plasma ambient containing hydrogen and an inert gas, and depositing a metallic material capable of forming silicide on the silicon surface. The metallic material is heated to form a metal silicide on the silicon surface.
In accordance with another aspect of the present invention, a method of fabricating a cobalt silicide structure on a silicon surface of a substrate is provided that includes exposing the silicon surface to a plasma ambient containing hydrogen and an inert gas wherein the substrate is not biased. Cobalt is deposited on the silicon surface. The substrate is heated to form cobalt monosilicide and heated again to convert the cobalt monosilicide to cobalt disilicide.
REFERENCES:
patent: 4994402 (1991-02-01), Chiu
patent: 5030590 (1991-07-01),
Besser Paul
Frenkel Austin
Sultan Akif
Advanced Micro Devices , Inc.
Anya Igwe U.
Honeycutt Timothy M.
Smith Matthew
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