Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
2002-05-17
2004-07-27
Nghiem, Michael (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
Reexamination Certificate
active
06768955
ABSTRACT:
BACKGROUND OF INVENTION
As shown in
FIG. 1
, a typical computer system
10
has, among other components, a microprocessor
12
, one or more forms of memory
14
, integrated circuits
16
having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths
19
, e.g., wires, buses, etc., to accomplish the various tasks of the computer system
10
.
In order to properly accomplish such tasks, the computer system
10
relies on the basis of time to coordinate its various operations. To that end, a crystal oscillator
18
generates a system clock signal (also referred to and known in the art as “reference clock”), SYS_CLK, to various parts of the computer system
10
. Modern microprocessors and other integrated circuits, however, are typically capable of operating at frequencies significantly higher than the system clock, and thus, it becomes important to ensure that operations involving the microprocessor
12
and the other components of the computer system
10
use a proper and accurate reference of time.
One component used within the computer system
10
to ensure a proper reference of time among a system clock and a microprocessor clock, i.e., “chip clock,” is a type of clock generator known as a phase locked loop, or “PLL”
20
. The PLL
20
is an electronic circuit that controls an oscillator such that the oscillator maintains a constant phase relative to a reference signal. Referring to
FIG. 1
, the PLL
20
has as its input the system clock, which is its reference signal, and outputs a chip clock signal, CHIP_CLK, to the microprocessor
12
. The system clock and chip clock have a specific phase and frequency relationship controlled by the PLL
20
. This relationship between the phases and frequencies of the system clock and chip clock ensures that the various components within the microprocessor
12
use a controlled and accounted for reference of time. When this relationship is not maintained by the PLL
20
, however, the operations within the computer system
10
become non-deterministic.
FIG. 2
shows a diagram of a typical PLL
20
. The PLL
20
includes a feedback loop that aligns the transition edge and frequency of a system clock, SYS_CLK
41
, and a feedback loop signal, FBK_CLK
40
. The PLL
20
adjusts the output frequency in order to zero any phase and frequency difference between the system clock
41
and the feedback loop signal
40
. The addition of a divide-by-N stage
39
in the feedback loop enables the PLL
20
to generate an output that has a frequency of N times the system clock
41
frequency. Multiplying the system clock
41
is necessary when a chip clock, CHIP_CLK
42
, must have a higher frequency than the system clock
41
. The PLL core
36
adjusts the output frequency in order to zero any phase and frequency difference between the system clock
41
and the feedback loop signal
40
. By adding the divide-by-N stage
39
, the chip clock
42
must be N times faster to allow the phase and frequency difference between the system clock
41
and the feedback loop signal
40
to zero. The PLL
20
may also have buffers
37
and
38
to drive a larger resistive and/or capacitive load. The buffers
37
and
38
are in the feedback loop so that any phase shift created by the buffers
37
and
38
is zeroed by the PLL core
36
.
One common performance measure for a PLL is jitter. Jitter is the time domain error from poor spectral purity of an output. In other words, in a repeated output pattern, such as a clock signal, a transition that occurs from one state to another does not happen at the same time relative to other transitions. Jitter represents the perturbations that result in the intermittent shortening or lengthening of signal elements of an output. The system clock may have jitter that may need to be filtered by the PLL. The PLL may need to follow and compensate for jitter at the PLL output.
Phase locked loops are basically second order feedback control systems. As such, the phase locked loop can be described in the frequency domain as having a damping factor and natural frequency. The damping factor and natural frequency are fixed by the selection of the PLL circuit parameters. The loop bandwidth is defined as the PLL input frequency at which the PLL output magnitude is 3 dB lower than the PLL output magnitude when the PLL input frequency is zero (DC). The loop bandwidth determines to a large degree the speed at which the phase locked loop can react to a disturbance. The PLL should have a low loop bandwidth so that input clock jitter is filtered. Power supply noise will, however, have a certain noise-versus-frequency characteristic. The PLL loop bandwidth may need to be increased to recover from the generation of output jitter caused by power supply noise.
SUMMARY OF INVENTION
According to one aspect of the present invention, an integrated circuit comprises: a power supply; a phase locked loop, operatively connected to the power supply, arranged to receive a system clock signal and output a chip clock signal, where the phase locked loop includes a phase frequency detector adapted to detect a phase difference between the system clock signal and a feedback clock signal, a charge pump (responsive to the phase frequency detector) adapted to output a current on a control signal, a bias generator (responsive to the control signal) adapted to generate a bias voltage, and a voltage controlled oscillator (responsive to the bias voltage) adapted to generate the chip clock signal; an adjustment circuit of which an output is operatively connected to the charge pump, where current output from the charge pump is responsive to the adjustment circuit; and a storage device adapted to store control information, where the adjustment circuit is selectively responsive to the control information.
According to another aspect, an integrated circuit comprises: power supply means for supplying power; phase locked loop means for receiving an input clock signal and outputting an output clock signal, where the power supply means is operatively connected to the power supply means, and where the phase locked loop means includes comparing means for detecting a phase difference between the input clock signal and a feedback clock signal, charge pumping means (responsive to the comparing means) for outputting a current on a control signal, bias generating means (responsive to the control signal) for generating a bias voltage, and oscillating means (responsive to the bias voltage) for outputting the output clock signal; adjusting means for adjusting the current output of the charge pumping means; and storing means for storing control information to which the adjusting means is selectively responsive.
According to another aspect, a method for post-fabrication treatment of a phase locked loop comprises: detecting a phase difference between an input clock signal and a feedback clock signal of the phase locked loop; generating a current on a control signal based on the detected phase difference; generating a bias voltage based on the control voltage; generating an output clock signal based on the bias voltage; selectively adjusting the current on the control signal; and storing at least a portion of control information determined from the selectively adjusting in a storage device, where the selectively adjusting is based on the at least a portion of the control information.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.
REFERENCES:
patent: 5631587 (1997-05-01), Co et al.
patent: 6049255 (2000-04-01), Hagberg et al.
patent: 6570421 (2003-05-01), Gauthier et al.
patent: 6570423 (2003-05-01), Trivedi et al.
patent: 6593784 (2003-07-01), Gauthier et al.
patent: 6597218 (2003-07-01), Gauthier et al.
“Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” by John G. Maneatis, IEEE Journal Solid-State Circuits, vol. 31, No. 11, Nov. 1996 (10 pgs).
Amick Brian W.
Gauthier Claude R.
Liu Dean
Trivedi Pradeep
Nghiem Michael
Osha & May L.L.P.
Sun Microsystems Inc.
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