Adjustable timing circuit of an integrated circuit

Details Adjustable timing circuit of an integrated circuit Adjustable timing circuit of an integrated circuit

2007-03-20

2007-03-20

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S189050

Reexamination Certificate

active

10931427

ABSTRACT:
An adjustable timing circuit includes non-volatile programmable fuses and adjustable delay elements. A propagation time of the delay element is selected with the non-volatile fuses. The delay element can include capacitors that are selectively coupled to a propagation path in response to the data stored in the fuse circuits. In one embodiment, data stored in the programmed fuses is copied to volatile latch circuits for use during operation of the timing circuit. The adjustable timing circuit can be provided in any integrated circuit, but is particularly useful in memory devices. The timing system allows for testing and fine-tuning signal processing in the integrated circuits.

REFERENCES:
patent: 5041886 (1991-08-01), Lee
patent: 5434523 (1995-07-01), Sundstrom
patent: 5537354 (1996-07-01), Mochizuki et al.
patent: 5600605 (1997-02-01), Schaefer
patent: 5666321 (1997-09-01), Schaefer
patent: 5751039 (1998-05-01), Kauffman et al.
patent: 5787457 (1998-07-01), Miller et al.
patent: 5845109 (1998-12-01), Suzuki et al.
patent: 5936903 (1999-08-01), Jeng et al.
patent: 5936977 (1999-08-01), Curchill et al.
patent: 5952857 (1999-09-01), Suzuki
patent: 5995438 (1999-11-01), Jeng et al.
patent: 6026465 (2000-02-01), Mills et al.
patent: 6067648 (2000-05-01), Hunter et al.
patent: 6073053 (2000-06-01), Dummermuth
patent: 6081477 (2000-06-01), Li
patent: 6108266 (2000-08-01), Weier et al.
patent: 6137133 (2000-10-01), Kauffman et al.
patent: 6141247 (2000-10-01), Roohparvar et al.
patent: 6157229 (2000-12-01), Yoshikawa
patent: 6219813 (2001-04-01), Bishop et al.
patent: 6262921 (2001-07-01), Manning
patent: 6385101 (2002-05-01), Chang et al.
patent: 2000251472 (2000-09-01), None
IBM Technical Disclosure Bulletin, “Delay Unit”. Sep. 1989. vol. 32 Issue 4A. pp. 408-409.
Keeth et al., “DRAM circuit design: a tutorial,” IEEE Press, 2001, pp. 16-23, 142-153.
Micron Semiconductor Products, Inc., “2Mb, Smart 5 BIOS-Optimized Boot Block Flash Memory,”Flash Memorywww.micron.com, copyright 2000, Micron Technology, Inc., pp. 1-12.
Micron, “16Mb: x16 SDRAM”Synchronous DRAM, www.micron.com, copyright 1999 Micron Technology, Inc. pp. 1-51.

Affiliated with

Also associated with

Rating

Adjustable timing circuit of an integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Adjustable timing circuit of an integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adjustable timing circuit of an integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3792497