Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1998-12-17
2001-01-23
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S083000, C326S086000, C365S189050
Reexamination Certificate
active
06177810
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor devices and more particularly, to an adjustable strength driver circuit for off chip drivers used in semiconductor memories and a method of adjustment.
2. Description of the Related Art
Semiconductor memories, such as dynamic random access memories (DRAMs), include an off chip driver (OCD) or an output buffer which provide a signal to be sent off the semiconductor chip during operation. A memory chip often includes an array of output buffers to permit simultaneous output of multiple databits. When several of the drivers of the array of buffers are in operation, the rise and/or fall time of the outgoing signals are slowed down. This is true for signals driven off the memory chip. The slow down is caused primarily by power and ground supply noise, and the resulting decrease in a gate to drain voltage (V
gs
) and drain to source voltage (V
ds
) of driver transistors of the buffer array. The load at the output is driven by less overdrive voltage V
gs
and less voltage difference V
ds
between source and drain of the driving transistor.
In DRAMs, there are typically between 4 to 32 output buffers, arranged in an array, and having a dedicated power supply. Package parasitics include inductances of a lead frame and a bond wire and capacitive loads including internal and external output loads as indicated in FIG.
1
. When, as a worst case, a majority of output buffers have to drive data of a same polarity (either “0” or “1”, single-sided), this causes a decrease of V
gs
and V
ds
. over the driving transistor. This slows down the rising or falling edge of the output signal and results in a lower speed performance of the DRAM. Although the rising or falling edge delay may be compensated for by increasing the width of the driving transistor, this cannot be performed dynamically and may therefore violate maximum slew rates in best cases.
Referring to
FIG. 1
, a typical output buffer
10
is shown having parasitic load
12
and capacitive loads
13
and
15
associated with lead frame and bond wire. Output buffer
10
includes two driving transistors
14
and
16
. Transistor
14
is driven by an n-logic signal while transistor
16
is driven by a p-logic signal. Transistor
14
has a source coupled to a first supply voltage (i.e., VSSD) while transistor
16
has a source coupled to a second supply voltage (VDDQ). When n-logic drives transistor
14
(which is an NFET pull transistor) to drive node OUT low, node
2
will temporarily bounce up (dI/dt noise, i.e., <U=L∃dI/dt where <U; is voltage variation caused by parasitic inductances L and dI/dt is the derivative of the current with respect to time). This voltage change caused by the inductance is not negligible and may significantly contribute to the decrease in V
gs
and V
ds
for transistor
14
. When a majority of output buffers in an array drive the same data (1's or 0's), this effect is further enhanced and causes a slowing down of the signal's OUT falling edge because V
gs
and V
ds
decrease further. Output timings become data pattern dependent resulting in reduced timing margins especially when the DRAM chip is operated at high frequencies.
Therefore, a need exists for an output buffer which dynamically adjusts the drive strength according to a data pattern to be output from an array of output buffers in its vicinity.
SUMMARY OF THE INVENTION
An output buffer, in accordance with the present invention includes a first driver circuit for coupling a first voltage to an output when the first driver circuit is turned on, and a second driver circuit for coupling a second voltage to the output when the second driver circuit is turned on. An input connects to the first and second driver circuits for turning the first and second driver circuits on and off according to a first input signal. An adjustment circuit is coupled to the first and second driver circuits for adjusting the strength of the first and second driver circuits according to a data pattern, the data pattern including the first input signal and input signals of a plurality of output buffers.
In alternate embodiments, the data pattern preferably includes bits, and the adjustment circuit adjusts the strength of the first and second driver circuits according to a number of bits having a same value. The first and the second driver circuits preferably include field effect transistors. The adjustment circuit preferably adjusts the strength of the driver circuits according to a graduated strength scale, the number of graduations being the number of inputs of the data pattern plus one. The adjustment circuit may overdrive the driver circuits to adjust the driver circuit strength. The adjustment circuit may include logic circuitry to adjust the first and second driver circuits. The plurality of output buffers may be disposed in an array of output buffers and may include adjacent output buffers.
Another output buffer includes a first driver device for coupling a first voltage to an output when the first driver device is turned on, and a second driver device for coupling a second voltage to the output when the second driver device is turned on. An input is connected to the first and second driver devices for turning the first and second driver devices on and off according to a first input signal. A NOR gate is provided having an output coupled to a first driver circuit for turning the first driver circuit on and off, the first driver circuit for coupling the first voltage to the output when the first driver circuit is turned on. A NAND gate is also provided having an output coupled to a second driver circuit for turning the second driver circuit on and off, the second driver circuit for coupling the second voltage to the output when the second driver circuit is turned on. The NOR gate and NAND gate receive an input data pattern such that upon logically combining the plurality of inputs the first and second driver circuits are turned on and off in conjunction with the first and second driver devices to adjust a driving strength to the output according to the data pattern, the data pattern including the first input signal and input signals of a plurality of output buffers.
In other embodiments, the data pattern preferably includes bits, and the driving strength to the output may be adjusted when the data pattern includes all bits having a same value. The first and the second driver devices preferably include field effect transistors. The first and second driver circuits include field effect transistors of the same type as the first and the second driver devices, respectively. The driver devices may include gates for activation of the driver devices, the gates being overdriven to adjust driver circuit strength. The plurality of output buffers may be disposed in an array of output buffers and may include adjacent output buffers. The first and second driver circuits may each include a control circuit which outputs a pulse to activate at least one driver device to assist in adjusting the driver strength of one of the first driver device and the second driver device.
A method for adjusting driver strength for output buffers includes the steps of providing an output buffer including a first driver circuit for coupling a first voltage to an output when the first driver circuit is turned on, a second driver circuit for coupling a second voltage to the output when the second driver circuit is turned on, an input connected to the first and second driver circuits for turning the first and second driver circuits on and off according to a first input signal and an adjustment circuit coupled to the first and second driver devices for adjusting the strength of the first and second driver circuits according to a data pattern, the data pattern including the first input signal and input signals of a plurality of output buffers, inputting the data pattern into the adjustment circuit, adjusting the strength of the first and second driver circuits according a number of high and low bits in the data pat
Chang Daniel D.
Paschburg Donald B.
Siemens Aktiengesellschaft
Tokar Michael
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