Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-08-07
2002-08-20
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S030000, C326S026000, C326S027000, C326S087000, C327S170000, C327S380000, C327S381000, C365S189050, C365S189110
Reexamination Certificate
active
06437600
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and in particular the present invention relates to data output drivers for high speed data transmissions.
BACKGROUND OF THE INVENTION
Integrated circuits typically include a number of input/output pins which are used for communication with additional circuitry. For example, an integrated memory device such as a dynamic random access memory (DRAM) includes both control inputs for receiving memory operation control signals, and data pins for bi-directional data communication with an external system or processor.
The data transmission rate of modem integrated circuits is primarily limited by internal circuitry operating speeds. That is, communication networks have been developed which can transmit signals between circuitry at a rate that is faster than the capacity of many integrated circuits. To address the need for faster circuits, a group of integrated circuits can be combined on a common bus. In this configuration, each integrated circuit operates in a coordinated manner with the other integrated circuits to share data which is transmitted at a high speed. For example, a group of memory devices, such as DRAMs, static RAMs, or read only memories (ROM), can be connected to a common data bus. The data rate of the bus may be substantially faster than the feasible operating speed of the individual memories. Each memory, therefore, is operated so that while one memory is processing received data, another memory is receiving new data. By providing an appropriate number of memory devices and an efficient control system, very high speed data transmissions can be achieved.
As the transmission rate of the data communication signals continues to increase, new circuitry and methods are needed to accurately transmit data from each integrated circuit. One proposed solution is a bus driver described in U.S. Pat. No. 5,254,883. This bus driver circuit uses parallel open-drain output transistors. The output transistors are fabricated in different sizes and selectively activated to control the bus current. This technique requires a relatively large number of output transistors to implement.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a high speed output driver circuit which is fully adjustable, and requires a limited number of output transistors.
SUMMARY OF THE INVENTION
The above mentioned problems with integrated circuit data transmission and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. An adjustable output driver circuit is described which includes an adjustable push-pull output, and an adjustable slew rate control.
In particular, the present invention describes an integrated circuit output driver circuit comprising a push-pull output comprising a pullup output transistor having a drain connected to a data communication line, and a pulldown output transistor having a drain connected to the data communication line. The integrated circuit output driver circuit further comprises a first adjustable circuit connected to a source of the pullup output transistor for adjusting a resistance between the drain of the pullup output transistor and a first reference voltage, and a second adjustable circuit connected to a source of the pulldown output transistor for adjusting a resistance between the source of the pulldown output transistor and a second reference voltage.
In an alternate embodiment, a synchronous memory device is described. The memory comprises an array of memory cells for storing data received on a data communication line, and an output driver circuit for outputting data read from the array of memory cells. The output driver circuit comprises a push-pull output comprising a pullup output transistor having a drain connected to the data communication line, and a pulldown output transistor having a drain connected to the data communication line. The output driver circuit further comprises a first adjustable circuit connected to a source of the pullup output transistor for adjusting a resistance between the source of the pullup output transistor and a first reference voltage, and a second adjustable circuit connected to a source of the pulldown output transistor for adjusting a resistance between the source of the pulldown output transistor and a second reference voltage. The first adjustable circuit comprises a first plurality of transistors connected in parallel and each having a drain connected to the source of the pullup transistor and the first reference voltage. The second adjustable circuit comprises a second plurality of transistors connected in parallel and each having a drain connected to the source of the pulldown transistor and the second reference voltage.
In yet another embodiment, an integrated circuit output driver circuit is described which comprises an output transistor having a drain connected to a data communication line, and an adjustable circuit connected to a source of the output transistor for adjusting a resistance between the source of the output transistor and a first reference voltage.
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Dorsey & Whitney LLP
Tan Vibol
Tokar Michael
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