Adjustable lock-in circuit for phase-locked loops

Details Adjustable lock-in circuit for phase-locked loops Adjustable lock-in circuit for phase-locked loops

2007-07-10

2007-07-10

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S017000, C331SDIG002

Reexamination Certificate

active

11102021

ABSTRACT:
The adjustable lock-in circuits basically include a sensor, a reference voltage, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. The sensor compares a feedback voltage with a reference voltage. If the sensing voltage does not reach the reference voltage, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the reference voltage. The time to reach the expected voltage level is simply equal to the charge stored at the filter divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all adjustable lock-in circuits provide an adjustable initial loop condition closer to the expected loop condition according to a targeted lock-in time. In addition, the initial loop condition is varied by changing the reference voltage level.

REFERENCES:
patent: 6229403 (2001-05-01), Sekimoto
patent: 2003/0214361 (2003-11-01), Nishikido
patent: 2005/0046497 (2005-03-01), Nakanishi

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