Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2000-06-23
2001-07-03
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S189050, C327S108000, C327S112000
Reexamination Certificate
active
06256235
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to compensating data signals applied to a memory bus and, more particularly, to tailoring the waveform of a data signal to compensate for signal degradation characteristics of a signal path.
DISCUSSION OF RELATED ART
Memory subsystems for computers and networking systems provide many memory devices on a common bus to allow larger storage and transmission capacities than can be obtained with a single memory device. The memory devices are multiplexed on to a single bus to reduce the pin count of a memory bus master or controller. Most of these systems require user upgradeable or replaceable components to allow future expansion or repair of the memory subsystems. Typically, these systems are upgraded on a module basis, where the memory module (e.g., a single or dual in-line memory module, SIMM or DIMM) has several memory devices on a small printed circuit board (PCB), and the module plugs into a connector that provides an electrical connection to the memory subsystem bus.
From a signal integrity standpoint, the provision of many memory devices on the bus can be problematic since these modules represent electrical stubs to the memory bus which cause reflections on the bus. These reflections degrade the signal integrity, and therefore, the maximum bandwidth or timing margin of the system. A very robust electrical design is required in these systems since the signal integrity must be acceptable for both lightly loaded systems, that is, only a small number of module slots are populated, as well as heavily loaded systems, and for every device on the bus. A spectral analysis of a system memory subsystem has shown that the frequency response varies significantly depending upon which memory device is being read or written.
One good example of a memory system that must carefully balance the design for different loading characteristics is a DDR SDRAM main memory system. In such a system, four memory slots can be provided with a bus data rate of 266 Mbps per pin. Balancing the design to be acceptable for lightly loaded and heavily loaded systems can be challenging due to the number of slots, and the large variance in combinations of loading. For example, a memory write to the first module closest to a controller with all four slots populated results in a large negative reflection on the bus, and a large undershoot of a data signal is seen at the memory devices of the first module. On the other hand, performing a write to this same location with only one module in the system results in a large overshoot of a data signal as seen at the memory devices. This demonstrates the challenge in balancing the design to work under both of these loading conditions, and at a fast data rate.
SUMMARY OF THE INVENTION
The present invention seeks to provide a more uniform frequency response for a device driver and a bus. Programmable pre-emphasis is applied to a bus driver output signal when a data signal is generated on the bus. The pre-emphasis can be tailored to the device receiving the data and the characteristics of the path between them such that a relatively clean square shaped pulse is seen at the data receiving device.
Pre-emphasis is achieved by changing the bus driver output signal waveform. In the case of a memory subsystem, the waveform can be tailored in accordance with signal degradation characteristics of the bus and memory device. As one example of use of the invention, the drive output waveform may be modified depending on the location of a memory device on the bus which will be receiving the data to compensate for signal degradation along the data path.
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Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Nguyen Tan T.
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