Adjustable delay circuit for setting the speed grade of a semico

Static information storage and retrieval – Read/write circuit – Signals

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Details

36518902, 327261, 327276, G11C 700, H03H 1126

Patent

active

060814624

ABSTRACT:
An integrated circuit having an adjustable delay circuit such that the timing characteristics of the integrated circuit can be adjusted. A method for adjusting the timing characteristics of the integrated circuit in order to insure that the integrated circuit meets the specifications of a lower speed grade in the event that the integrated circuit fails the specifications of a targeted speed grade.

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