Adiabatic MOS logic and power supplying method and apparatus

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor

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326 93, 326 21, H03K 1716

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057010935

ABSTRACT:
A plurality of stages of MOS gate circuits are connected in series and are driven with a 2-phase AC power source. The alternating speed of the power source is slower than the operation speed of internal circuit elements of the MOS gate circuits. A cutoff device such as a transistor is arranged on each side of each of the MOS gate circuits and is connected to the power source. The cutoff devices of each MOS gate circuit are conductive only when one phase of the power source is at high potential and the other at low potential. When the MOS gate circuit of a given stage (N.sub.i) is inactive, the MOS gate circuit of the next stage (N.sub.i+1) holds charge, to reduce an energy loss.

REFERENCES:
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patent: 5459414 (1995-10-01), Dickinson
patent: 5508639 (1996-04-01), Fattaruso
Mead and Conway, Introduction to VLSI Design, Addison-Wesley Pub. Co., Reading, Mass., pp. 338-341, Oct. 1980.
Seitz et al, "Hot-Clock nMOS", 1985 Chapel Hill Conference on VLSI, pp. 1-17, 1985.
Younis et al, "Practical Implementation of Charge Recovering Asymptotically Zero Power CMOS", MIT, Cambridge, Mass., pp. 1-15, Oct. 1992.
Hinman et al., "Power Dissipation Measurements on Recovered Energy Logic", IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 19-20, 1994.
Kramer et al., "Adiabatic Computing with the 2N-2N2D Logic Family", IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 25-26, 1994.

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