Adiabatic dynamic precharge boost circuitry

Details Adiabatic dynamic precharge boost circuitry Adiabatic dynamic precharge boost circuitry

1993-05-28

1995-12-05

Hudspeth, David R.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326123, H03K 19094

Patent

active

054732700

ABSTRACT:
Power dissipation in precharge paths used in adiabatic dynamic logic circuitry is reduced by a precharge boost circuit which decreases the impedance between a clock node and an output node in such logic circuitry and thereby increases the charging current from a clock signal generator. In one example, a diode used to precharge an output node in adiabatic dynamic logic circuitry is selectively shorted by a controllable switch selectively connected in parallel with the diode when the output node is to be precharged.

REFERENCES:
Koller and Athas, Adiabatic Switching, Low Energy Computing, and the Physics of Storing and Erasing Information, USC Information Sciences Institute, Marina Del Ray, Calif., Aug., 1992.
Younis and Knight, Practical Implementation of Charge Recovering Asymptotically Zero Power CMOS, Massachusetts Institute of Technology, Cambridge, Mass., Oct. 1992.
Hinman and Schlecht, Recovered Energy Logic--A Highly Efficient Alternative to Today's Logic Circuits, Massachusetts Institute of Technology, Cambridge, Mass., Jan. 1993.
Merkle, Reversible Electronic Logic Using Switches, submitted to Nanotechnology for publication Sep., 1992.

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