Adiabatic dynamic logic

Details Adiabatic dynamic logic Adiabatic dynamic logic

1993-05-28

1995-10-17

Hudspeth, David R.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 98, H03K 1716

Patent

active

054594146

ABSTRACT:
A novel family of adiabatic dynamic logic gates can have power*delay products at least an order of magnitude or more below that which was possible in previous families of logic gates. No complex circuitry or unusually configured devices are needed to implement this logic family. In particular, this logic family requires fewer devices and less area per logic gate as compared with ordinary CMOS logic circuitry. This is unlike previous reversible logic proposals which required large numbers of transistors per gate. This logic circuitry can operate from very low supply voltages and need not be optimized for a particular voltage. This logic does not suffer from crowbar currents usually found in prior circuitry such as CMOS logic. Logic levels are regenerated at nearly every stage unlike some previous schemes which reduce energy dissipation only by sacrificing logic levels. At each stage in a calculation, this logic recovers a substantial amount of the energy used to perform the calculation and returns it to the power supply.

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patent: 5121003 (1992-06-01), Williams
patent: 5208490 (1993-05-01), Yetter
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"Low-Power CMOS Digital Design", A. P. Chandrakasan, et al., IEEE Journal of Solid-State Circuits, vol. 27, No. 4, Apr. 1992, pp. 473-484.
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"Adiabatic Switching, Low Energy Computing and the Physics of Storing and Erasing Information", J. G. Koller, et al., USC Information Sciences Institute, Aug. 5, 1992, pp. 1-5.
"Hot-Clock nMOS", C. L. Seitz, et al., 1985 Chapel Hill Conference on VLSI, pp. 1-17.
"Practical Implementation of Charge Recovering Asymptotically Zero Power CMOS", S. G. Younis, et al., Artificial Intelligence Laboratory, Massachusetts Institute of Technology, Oct. 9, 1992, pp. 1-15.

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