Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
2001-11-27
2002-11-05
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S773000, C257S783000, C156S295000, C156S291000
Reexamination Certificate
active
06476504
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to a die attach method of an assembly process of semiconductor packages, and more particularly to an adhesive pattern for use in the die attach method.
2. Description of the Related Art
Generally, an assembly process of semiconductor packages includes: dicing of a wafer including a number of semiconductor chips into individual semiconductor chips; attaching each semiconductor chip onto means for supporting chips, i.e., a substrate or a lead frame using an adhesive; electrically connecting each semiconductor chip to the supporting means; encapsulating each chip against a portion of the supporting means.
In the die attach process, the substrate or the lead frame is placed at a predetermined position by a transferring unit, and an adhesive is applied to the metal paddle of the substrate or the die pad of the lead frame by a dispenser in the die-bonding equipment. Then, an automatic pick and place machine picks up a semiconductor chip and accurately places the chip to the metal paddle or the die pad with the pre-dispensed adhesive. The final step of the die-bonding process is curing of the adhesive.
Traditionally, the epoxy is dispensed on the metal paddle of the substrate or the die pad or the lead frame in a predetermined dot or line pattern. Typically, both of the metal paddle and the die pad have a uniform surface. Therefore, conventional adhesive patterns can adequately attach the chip to the die pad or the lead frame without causing voids or the problem of adhesive bleed.
However, when the conventional adhesive patterns are used for overlaying the surface of a non-uniform substrate, voids are often unavoidable. When the voids are generated in the adhesive, moisture from the environment easily penetrates into the adhesive and accumulates in the voids. Once moisture accumulates in the voids, rapid temperature ramp-up, e.g., in the curing process, will cause the moisture to vaporize and expand, thereby inducing hydrothermal stresses in the area around the voids. Furthermore, when a semiconductor chip is mounted to the uneven surface applied with the conventional adhesive patterns, the adhesive tends to bleed out of the die perimeter thereby contaminating chip connection pads disposed nearby, which is fatal to surface bondability thereof.
Therefore, a need exists in the semiconductor industry for an adhesive pattern suitable for a non-uniform substrate which overcomes, or at least reduces the above-mentioned problems of the prior art.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide an adhesive pattern suitable for a non-uniform substrate which avoids void formation in the adhesive while preventing the adhesive bleed.
It is another object of the present invention to provide a die attach method utilizing a double-k adhesive pattern which avoids void formation in the adhesive while preventing the adhesive bleed.
In accordance with at least the above objects, the present invention discloses a double-k adhesive pattern for attaching a semiconductor chip onto a non-uniform substrate. The double-k pattern includes a longest major line and four shorter lines connected to the major line. The non-uniform substrate has a conductive circuit and a solder mask formed on the substrate including the circuit. The substrate has a die covering region for receiving the semiconductor chip. The conductive circuit of the substrate comprises a plurality of conductive traces unequally distributed on the die covering region. The double-k adhesive pattern of the present invention is applied onto the non-uniform substrate by a dispenser of a die-bonding equipment in a manner that the area on the substrate defined between the major line and the border of the die covering region has a trace density lower than the other area on the substrate.
The present invention further provides a die attach method comprising: (a) providing a substrate including a conductive circuit and a solder mask formed over the substrate including the circuit with a substantially uniform thickness wherein areas on the conductive circuit adapted for electrical connection are exposed from the solder mask, the substrate having a die covering region for receiving a semiconductor chip, the conductive circuit having at least a portion formed on the die covering region with an unequally distributed layout pattern; (b) forming an adhesive on the substrate in a double-k pattern; (c) placing the semiconductor chip onto the adhesive; and (d) curing the adhesive.
REFERENCES:
patent: 5423889 (1995-06-01), Colquitt et al.
patent: 5681757 (1997-10-01), Hayes
patent: 6174406 (2001-01-01), Gaynes et al.
Onodera et al., US Patent Publication 2001/0013641, Aug. 16, 2001.
Chu Fu Tang
Teng Ji Ping
Advanced Semiconductor Engineering Inc.
Dykema Gossett PLLC
Talbott David L.
Zarneke David A.
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