Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2000-02-16
2004-03-23
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S723000, C257S778000, C257S685000, C257S686000
Reexamination Certificate
active
06710454
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to packaging of semiconductor devices and, more specifically, to an improved flip chip package and method of pre-packaging a flip chip.
BACKGROUND OF THE INVENTION
As demand for smaller, more powerful electronic devices grows, semiconductor manufacturers are constantly attempting to reduce the size and cost of not only semiconductor devices themselves but also semiconductor packaging. Smaller packages equate with higher semiconductor mounting densities and higher mounting densities allow for more compact and yet more capable devices.
With conventional packaging methods, a semiconductor die or “chip” is singulated from the silicon wafer and is encapsulated in a ceramic or plastic package having a number of electrical leads extending therefrom. The leads permit electrical connection between external components and the circuits on the die. Although these packages have proven reliable, they are generally many times larger than the actual die. In addition, the configuration of these packages typically yields only a limited number of leads. For these reasons, conventional packaging techniques are not particularly adaptable to high density packaging.
Accordingly, more efficient chip packages have been developed. One such package is the “pin grid array” or PGA which utilizes a series of pin conductors extending from the face of the package. While PGAs provide increased electrical interconnection density, the pins forming the PGA are fragile and easily bent. In addition, the PGA is relatively expensive to produce and of limited value when the package is to be permanently mounted.
Similar to the PGA are various flip chip packages including the “ball grid array” or BGA. Instead of pins, the BGA has an array of solder bumps or balls attached to the active face of the package in a process called “bumping.” The array of solder bumps is adapted to mate with discreet contacts on a receiving component. The package may be subsequently heated to partially liquefy or “reflow” the bumps, thus forming electrical connections at the discreet locations. This technology is frequently referred to as “flip chip” because the solder balls are typically secured to the semiconductor package wherein the package is then “flipped” to secure it to the receiving component. The present invention is directed primarily to flip chip packaging technology and the remainder of this discussion will focus on the same.
While flip chip processes have proven effective, problems remain. For instance, conventional flip chip technology requires an underfill layer between the semiconductor package and the receiving substrate. The underfill material reduces stress on the solder bumps caused by thermal mismatch between the semiconductor package and substrate. The underfill layer further provides insulation between the device and substrate and prevents creep flow at the solder interface. Without the underfill layer, repeated thermal cycling constantly stresses the solder interconnections, potentially leading to failure.
Unfortunately, the underfill process is time consuming and expensive. For example, the equipment used to dispense the underfill must precisely maintain the viscosity of the material, dispensing it at a particular flow rate and within a predetermined temperature range. Further, the underfill process cannot be applied until the package is secured to its receiving substrate. Accordingly, the chip package and substrate design must permit the dispensing equipment direct access to the package/substrate interface. And still further, since the underfill material is distributed via capillary action, the time required to complete the underfill operation can be significant.
One method which avoids the use of underfill material involves the use of a resilient retaining member which supports a series of solder preforms therein. The retaining member is sandwiched between conductive elements such that the preforms effect electrical connection therebetween. Like underfill, however, the retaining member/solder preform is only utilized during actual surface mounting of individual chips.
While underfill processes as well as retaining member/preforms are more than adequate in many applications, current trends in IC fabrication favor completing more and more process steps—many of which would not normally occur until after die singulation—at the wafer level. Wafer level processing is advantageous over conventional methods as it allows multiple ICs (equal to the number of die on the wafer face) to be processed simultaneously rather than serially as typically required after die singulation. Accordingly, the time required to produce a given IC device can be dramatically reduced.
While some processes lend themselves to wafer level processing, known packaging methods such as underfill and retaining member/preform methods unfortunately do not. Thus, what is needed is a flip chip package that can be assembled at wafer level. What is further needed is a package that avoids the problems with underfill materials including troublesome dispensing and assembly cycle times. The present invention is directed to a package and method that addresses these issues.
SUMMARY OF THE INVENTION
To address these problems, an electronic apparatus was devised that, in one embodiment, includes a first semiconductor device having a first side and an opposing second side. The first side of the first device includes a first array of connection pads. Also included is a flip chip adhesive layer covering the first side. The adhesive layer has a first array of openings extending through the layer where the first array of openings is substantially aligned with the first array of connection pads. The apparatus further includes an electrically conductive material substantially filling the first array of openings.
Another embodiment relates to a method of packaging a die at wafer level. The method includes applying a flip chip adhesive to a first side of a finished wafer, the wafer having at least one die thereon. An array of openings is then created in the adhesive. The array of openings provides access to an array of connection pads on each die. The array of openings is then substantially filled with an electrically conductive material.
In yet another embodiment, an electronic apparatus is provided having a first semiconductor device and a second semiconductor device. The first semiconductor device has a first side and a second side where the first side includes a first array of connection pads. The second semiconductor device also has a first side comprising a second array of connection pads. The second side of the first semiconductor device is coupled to the first side of the second semiconductor device such that the second array of connection pads is adjacent the first array of connection pads.
In still yet another embodiment, a semiconductor wafer is provided. The wafer includes at least one die formed on a face of the wafer where the die has an array of connection pads electrically coupled to circuits on the die. Furthermore, the wafer includes an adhesive layer covering the face of the wafer. The adhesive layer has an array of openings where the array of openings are adapted to provide access to the array of connection pads.
A method of packaging two or more semiconductor devices is also provided. In this embodiment, a second side of a first semiconductor device is attached to a first side of a second semiconductor device such that a first array of connection pads located on a first side of the first semiconductor device is adjacent to a second array of electrical connection pads located on the first side of the second semiconductor device. An adhesive layer is applied over the first side of the first semiconductor device and the first side of the second semiconductor device.
An electronic system is provided in still yet another embodiment. The system includes a processor and a pre-packaged flip chip. The pre-packaged flip chip includes a first semiconductor device having a first side and a second side where the first s
Fahmy Wael
Micro)n Technology, Inc.
Nguyen DiLinh
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
Adhesive layer for an electronic apparatus having multiple... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Adhesive layer for an electronic apparatus having multiple..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adhesive layer for an electronic apparatus having multiple... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3256246