Addressing system in a multi-port RAM having main and cache memo

Details Addressing system in a multi-port RAM having main and cache memo Addressing system in a multi-port RAM having main and cache memo

1998-02-04

2000-07-11

Robertson, David

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711118, 711154, G06F 1202, G06F 1300

Patent

active

060887605

ABSTRACT:
A multi-port memory chip having a DRAM main memory and a SRAM cache memory coupled via a global bus. An addressing system enables the user to perform data transfers between external data ports and the SRAM concurrently with data transfers between the DRAM and the SRAM. To support DRAM operations, DRAM address pins on the memory chip select a data block in the DRAM, and indicates a SRAM line for receiving or transferring data. To support SRAM operations, SRAM address pins determine addressed line and word in the SRAM. To reduce the number of pins on the memory chip the DRAM address pins and SRAM address pins are used for supplying commands that define various memory operations.

REFERENCES:
patent: 5544121 (1996-08-01), Dosaka et al.
patent: 5546343 (1996-08-01), Elliott et al.
patent: 5561781 (1996-10-01), Braceras et al.
patent: 5566318 (1996-10-01), Joseph

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