Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2005-09-06
2005-09-06
Huynh, Kim (Department: 2182)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C710S003000, C709S213000
Reexamination Certificate
active
06941440
ABSTRACT:
A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.
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Gulati Manu
Kelly James D.
Moll Laurent R.
Oner Koray
Rowlands Joseph B.
Broadcom Corporation
Garlick Harrison & Markison LLP
Huynh Kim
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