Addressing of redundant columns and rows of an integrated circui

Details Addressing of redundant columns and rows of an integrated circui Addressing of redundant columns and rows of an integrated circui

1988-03-02

1990-08-07

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Bad bit

371 103, G11C 800

Patent

active

049473751

ABSTRACT:
A method for the addressing of redundant elements of an integrated circuit memory is disclosed. This memory comprises an array of row memory elements and column memory elements, respectively addressable by row addresses and column addresses, at least one battery of fuses to store the address of a faulty element of the memory. The method consists:

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Patent Abstracts of Japan, vol. 8, No. 151 (P-286) [1588], 13 Juillet 1984; and JP-A-59 48 898 (Hitachi Seisakusho K.K.), 21-03-1984.
Processing of the IEEE, vol. 74, No. 5, Mai 1986, pp. 684-698, IEEE, New York, US; W. R. Moore: "A Review of Fault-Tolerant Techniques for the Enhancement of Integrated Circuit Yeild", p. 684, colonne 2, ligne 22-colonne 2, ligne 16.

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