Addressing of memory matrix

Details Addressing of memory matrix Addressing of memory matrix

2001-07-06

2004-10-12

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S189011

Reexamination Certificate

active

06804138

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of driving a passive matrix-addressable display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis.
BACKGROUND INFORMATION
Passive matrix addressing implies the use of two sets of parallel electrodes that cross each other, typically in orthogonal fashion, creating a matrix of crossing points that can be individually accessed electrically by selective excitation of the appropriate electrodes from the edge of the matrix. Advantages of this arrangement include simplicity of manufacture and high density of crossing points, provided the functionality of the matrix device can be achieved via the two-terminal connections available at each crossing point. Of particular interest in the present context are display and memory applications involving matrices where the electrodes at each crossing point sandwich a material in a capacitor-like structure, henceforth termed a “cell”, and where the material in the cells exhibits polarizability and hysteresis. The latter property confers non-volatility on the devices, i.e. they exhibit a memory effect in the absence of an applied external field. By application of a potential difference between the two electrodes in a given cell, the material in the cell is subjected to an electric field which evokes a polarization response, the direction and magnitude of which may be thus set and left in a desired state, representing e.g. a logic “0” or “1” in a memory application or a brightness level in a display application. Likewise, the polarization status in a given cell may be altered or deduced by renewed application of voltages to the two electrodes addressing that cell.
Examples of passive matrix devices employing ferroelectric memory substances can be found in the literature dating back 40-50 years. Thus, E. G. Merz and J. R. Anderson described a barium titanate based memory device in 1955 (W. J. Merz and J. R. Anderson, “Ferroelectric storage devices”, Bell.Lab.Record. 1, pp. 335-342 (1955)), and similar work was also reported by others promptly thereafter (see, e.g. C. F. Pulvari “Ferroelectrics and their memory applications”, IRE Transactions CP-3, pp. 3-11 (1956), and D. S. Campbell “Barium titanate and its use as a memory store”, J. Brit. IRE 17 (7) pp. 385-395 (1957)). An example of a passive matrix addressed display rendered non-volatile by a ferroelectric material can be found in U.S. Pat. No. 3,725,899 (W. Greubel) filed in 1970.
In view of its long history and apparent advantages, it is remarkable that the passive matrix addressing principle in conjunction with ferroelectrics has not had a greater impact technologically and commercially. While important reasons for this may be traced back to the lack of ferroelectric materials that satisfy the full range (technical and commercial) of minimum requirements for the devices in question, a major factor has been certain inherent negative attributes of passive matrix addressing. Prominent among these is the problem of disturbing non-addressed crossing points. The phenomenon is well recognized and extensively discussed in the literature, both for displays and in memory arrays. Thus, the basics shall not be discussed here, but the reader is referred to, e.g.: A. Sobel: “Some constraints on the operation of matrix displays”, IEEE Trans.Electron Devices (Corresp.) ED-18, p. 797 (1971), and L. E. Tannas Jr., “Flat panel displays and CRTs”, pp. 106 & seq., (Van Nostrand 1985). Depending on the type of device in question, different criteria for avoiding or reducing disturbance of non-addressed crossing points can be defined. Generally, it is sought to lower the sensitivity of each cell in the matrix to small-signal disturbances, which can be achieved by cells that exhibit a non-linear voltage-current response, involving e.g. thresholding, rectification and/or various forms of hysteresis.
Although general applicability is claimed for the present invention, particular focus shall be directed towards ferroelectric memories, where a thin film of ferroelectric material is stimulated at the matrix crossing points, exhibiting a hysteresis curve as illustrated generically in FIG.
1
. Typically, writing of a bit is accomplished by applying a voltage differential across the film at a crossing point, causing the ferroelectric to polarize or switch polarization. Reading is analogously achieved by applying a voltage of a given polarization, which either causes the polarization to remain unchanged after removal of the voltage or to flip to the opposite direction. In the former case, a small current will flow in response to the applied voltage, while in the latter case the polarization change causes a current pulse of magnitude larger than a predefined threshold level. A crossing point may arbitrarily be defined as representing a “0” bit in the former case, a “1” bit in the latter.
A material with hysteresis curve as shown in
FIG. 1
will change its net polarization direction upon application of a field that exceeds V
C
. However, partial switching shall take place upon application of voltages below this value, to an extent depending on the material in question. Thus, in a matrix with a large number of crossing points, repeated stimuli of non-addressed crossing points may ultimately degrade the polarization states in the matrix to the point where erroneous reading results. The amount and type of stimulus received by non-addressed crossing points in a cross-bar passive matrix during write and read operations depends on how the voltages are managed on all addressing lines in the matrix during these operations, henceforth termed the “pulsing protocol”. The choice of voltage pulsing protocol depends on a number of factors, and different schemes have been proposed in the literature, for applications involving memory materials exhibiting hysteresis. Examples of prior art shall now be given.
U.S. Pat. No. 2,942,239 (J. P. Eckert, Jr. & al.) discloses pulsing protocols for memory arrays with magnetic cores, each with a magnetic hysteresis curve analogous to the ferroelectric one shown in FIG.
1
. Although claiming general applicability for memory elements exhibiting bistable states of remnant polarization, including ferroelectrics, their invention contains only specific teachings on magnetic data storage where separate contributions to the total magnetic flux in each cell are added or subtracted from several independent lines intersecting in each cell. This is reflected in how cells are linked up in the proffered embodiments, with a readout protocol providing superposition of a slow, or “background” biasing stimulus being applied to all or a subset (e.g. a column or a row) of the cells in the matrix, and with a fast selection pulse being applied between the crossing lines containing the addressed cell. No teachings are given on efficient voltage protocols for two-terminal, capacitor-like memory cells combining high speed, random access to data with restoration of the destructively read information.
U.S. Pat. No. 3,002,182 (J. R. Anderson) concerns the problem of polarization loss by partial switching of ferroelectric memory cells in passive matrix addressed arrays of ferroelectric-filled capacitors. To reduce the partial switching polarization loss during writing, this patent teaches the use of simultaneous application of addressing pulses to an addressed row and column such that the former executes an electrical potential swing of typically +2V
s
/3 to +3V
s
/4 (where V
s
is the nominal switching voltage) while the latter swings to a negative value sufficient for the potential difference between the electrodes at the selected crossing point to reach the value V
s
. With the remaining columns being switched to a potential in the range +V
s
/3 to +V
s
/4, only the selected cell in the matrix is subjected to a significant switching field, and partial switching at the other crossing points is strongly reduced (the reduction depends on the material properties of the ferroelectric, in particular the s

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