Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1996-08-09
1999-01-12
Lane, Jack A.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711209, G06F 1210
Patent
active
058601449
ABSTRACT:
An addressing method and system for accessing a very large size physical buffer by a number of processes. The novel system is applicable within a computer system having an n-bit computer operating system (e.g., where n is 16, 32, 64, etc.). The addressing method allocates a relatively small window of virtual address space, for each software process, which is used to access the very large physical buffer using a relatively small amount of operating system memory overhead. A page frame number (PFN) table of the system address space maintains a listing of physical memory pages used to define the very large physical buffer. The PFN table is used by each process to translate between a relative page number (RPN) and an address of a physical memory page containing the record. The virtual address space ("window") of each process is used to access the physical memory buffer and contains a hash table, a virtual access control block (VACB) free list, and a VACB table. Entries of the VACB table indicate addresses of virtual memory for the process. Each process also has an associated private page table entry (PTE) table which maintains a mapping between its virtual pages and the physical pages. To map a record, its RPN is determined and used to obtain the address of the physical page(s) in which the record resides. The free list supplies an entry of the VACB table containing a virtual address for the record. The virtual address and the physical address are mapped into the PTE table.
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Anderson Richard
Arun Gopalan
Frank Richard
Klein Stephen
Lane Jack A.
Oracle Corporation
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